请问怎么才能在Spartan 6 Deserialier上抖动简单地反序列化6个？

9，
依靠，
容许抖动取决于从数据中恢复时钟。
对于恢复时钟的数据，最坏情况下的抖动是700 ps还是+/- 350 ps？
如果是这样，那么给定数据波形的形状，这可能都在眼睛的开口内（数据稳定且有效）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

9,
 
Depends,
 
Tolerating jitter depends on your clock recovery from the data.  Is the worst case jitter 700 ps, or +/- 350 ps for the data from your recovered clock?
 
If so, then given the shape of the data waveform, that might be all within the opening iof the eye (where the data is stable and valid).
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

亲爱的奥斯汀，
我在论坛中找到了这个。
解串器的输入数据和输入时钟之间是否存在相位要求？
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Problem-with-phase-detector-on-Spartan-6/td-p/77309
11-02-2011 01:39 AM
你好约翰，
是的，这是可以预料的。
如果采样时钟和数据之间的关系大约为180度，则会发生环绕并导致数据丢失。
问候
缺口
Xilinx员工
....



以下为原文

Dear Austin,I found this in the forum. Is there a phase requirement between the incoming data and incoming clock for the deserializer?http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Problem-with-phase-detector-on-Spartan-6/td-p/7730911-02-2011 01:39 AM Hello John,Yes, this is to be expected. If the realtionship between the sampling clock and data is around 180 degrees then wraparound and data loss will occur.RegardsNickXilinx Employee....

亲爱的奥斯汀，
问题
我们有8个LVDS数据通道，560Mbps和1个时钟280MHz（DDR），我们将其反序列化为14比1
8个频道中的7个无误地工作。
具有最大延迟的1个通道在来自bitlip的50-100个时钟周期之后产生1位移位错误，其被锁定。
实验
如果我在IDELAY VALUE上设置延迟（时钟，从属，iodelay属性），我可以将问题推送到其他数据通道
我们的想法
我们认为相位检测包含在内并因延迟和抖动而使数据位移一位
问候
9



以下为原文

Dear Austin,
 
problem
we have 8 LVDS data channels, 560Mbps and 1 clock 280MHz (DDR) that we deserialize 14 to 1
7 out of 8 channels work without errors.
1 channel with most delay creates 1 bit shift error, after 50-100 clock cycles from bitslip, which is locked.
 
experiment
I can push the problem to the other data channels if I put a delay on IDELAY VALUE  (clock, slave, iodelay attribute)
 
what we think
We think phase detection wraps around and makes one bit data shift due to delay and jitter
 
 
regards
9

我不想干涉9和奥斯汀之间的交流。
以下问题的答案可能有助于奥斯汀帮助您。
9的问题：
280MHz时钟如何接收并分配到8个输入数据通道？
所有8个输入通道都在Spartan-6设备的同一边缘吗？
所有8个输入通道是否都在Spartan-6设备的同一半边缘？
所有8个输入通道是否共享公共BITSLIP逻辑，还是每个数据输入通道都有独立的BITSLIP状态机？
相位检测（使用IDELAY）是用于输入数据通道，还是使用固定延迟（使用IDELAY）？
是否测量了8个数据通道之间的板载时序偏差？
如果是，那么FPGA输入端的8个数据通道的时序如何匹配？
- 鲍勃埃尔金德
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以下为原文

I do not want to interfere in the exchange between 9 and Austin.  The answers to the following questions might help Austin to help you.
 
Questions for 9:
 

• How is the 280MHz clock received and distributed to the 8 input data channels?
  

• Are all 8 input channels on the same edge of the Spartan-6 device?
  

• Are all 8 input channels on the same half-edge of the Spartan-6 device?
  

• Do all 8 input channels share common BITSLIP logic, or is there independent BITSLIP state machine for each data input channel?
  

• Is phase detection (with IDELAY) used for input data channels, or is fixed delay (with IDELAY) used?
  

• Has on-board timing skew between the 8 data channels been measured?  If yes, how well matched are the timings of the 8 data channels at the input to the FPGA?
  

-- Bob Elkind
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