I am working on a source synchronous serial interface. As I am outputing serial data, I am intersted in the OFFSET OUT Timing. I am using a IOB register for data and a ODDR2 (180 degree phase shifted) for the clock. The clock that clocks the ODDR2 is generated using a MMCM.
I tried different OFFSET OUT constraints but the constraint would always be ignored. However, I came across this answer and modelled my constraints based on the answer record.
NET "up_clk" TNM_NET = up_clk;
TIMESPEC TS_up_clk = PERIOD "up_clk" 12.531 ns HIGH 50%;
NET "dn_d" TNM = downlink_data_clk;
NET "dn_clk" TNM = downlink_data_clk;
INST "downlink_head/serial_tx/o_ser_data" TNM = downlink_data_clk_reg;
INST "downlink_head/serial_tx/serial_clock" TNM = downlink_data_clk_reg;
TIMEGRP "downlink_data_clk" OFFSET = OUT AFTER "up_clk" REFERENCE_PIN "dn_clk" TIMEGRP "downlink_data_clk_reg";
The constraints are not ignored anymore. However, I am not sure how to interpret the results. Can you please explain or point me to any documentation that explains the results.
