请问selectIO向导假设输入时钟是280MHz吗？

我使用selectiO向导4.1的相机链接接收器模板在spartan 6上生成ip内核。我的问题是，似乎ip内核中的输入时钟（CLK_IN_P＆amp; CLK_IN_N）不是普通平板lcd lvds时钟的时钟。
例如，SVGA的时钟对频率为40MHz，串行数据频率为280MHz。
但是selectIO向导假设输入时钟是280MHz？
因为我看到它在源代码中将输入时钟分为1/7。



以下为原文

I use camera  link receiver template of selectIO wizard 4.1 to generate a ip core on spartan 6. my question is that it seems the input clock in the ip core (CLK_IN_P & CLK_IN_N) is not the very clock of  normal flat lcd lvds clock. for example,  the frequency of clock pair is 40MHz for SVGA and the serialized data frequency is 280MHz. but selectIO wizard assumes the input clock is 280MHz? because I saw it divided the input clock to 1/7 in the source code.