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我正在构建一个FPGA电路,它将接受并行16位原始数字视频输入并串行化为平板屏幕的LVDS输入。 像素速率为40Mhz,LVDS为280MHz,序列化速率为1:7。 我可以想到2个时钟选项,但我不确定哪个是最好的。 1。 时钟取自40Mhz的像素时钟,内部DCM将其乘以7以产生280Mhz,逻辑全部以此速度运行。 2.要使用28Mhz的外部时钟,使用DCM x10创建280Mhz,然后对视频输入进行过采样以确定数据转换。 所以我想我想说的是,最好是使用像素时钟来驱动电路或使用外部时钟并过度采样视频输入。 任何帮助将不胜感激,谢谢。 史蒂夫 以上来自于谷歌翻译 以下为原文 Hi I am building an FPGA circuit that will accept a parallel 16bit raw digital video input and serialize to an LVDS input for a flat panel screen. The pixel rate is 40Mhz and the LVDS is 280MHz, serializes is a t a rate of 1:7. I can think of 2 clocking options but i'm unsure which will be best. 1 . The clock is taken from the pixel clock at 40Mhz, an internal DCM multiplies this by 7 to produce 280Mhz, the logic all runs at this speed. 2. To use an external clock of 28Mhz, use a DCM x10 to create 280Mhz, the video input is then over sampled to determine the data transitions. So i guess what i'm trying to say is, would it best to use the pixel clock clock to drive the circuit or use an external clock and over sample the video input. Any help would be appreciated, thanks. Steve |
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嗨鲍勃
感谢您的快速回复。 我正在使用Spartan 6部分,所以我将查看OSERDES2原语。 我还需要运行一些逻辑,在没有检测到视频输入时创建一个闪屏。 当检测到像素视频时钟时,启动屏幕禁用并且视频被序列化并输出。 运行此闪屏并使用外部时钟驱动LVDS逻辑同时连续采样视频像素时钟以进行活动是否合理,然后在检测到像素时钟切换输出时切换到视频? 史蒂夫 以上来自于谷歌翻译 以下为原文 Hi Bob Thanks for the speedy reply. I am using a Spartan 6 part so i'll look into the OSERDES2 primitive. I also need to run some logic which creates a splash-screen when no video input is detected. When the pixel video clock is detected the splash screen disables and the video is serialized and output. Would it be sensible to run this splashscreen and drive the LVDS logic with an external clock while continuously sampling the video pixel clock for activity, then switch to the video when the pixel clock is detected switch the outputs? Steve |
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运行此闪屏并使用外部时钟驱动LVDS逻辑同时连续采样视频像素时钟以进行活动是否合理,然后在检测到像素时钟切换输出时切换到视频?
如果输入视频像素时钟不是恒定时钟源,那么您显然必须提供备用时钟。 有几种设计方法可以适用于您描述的应用程序 - 只需选择一个并进行前进。 就个人而言,我不会切换时钟源。 我将为内部逻辑提供一个固定的固定时基,并设计一条路径,用于将输入视频信号桥接到内部时基。 典型实现使用过采样(和输入像素时钟边沿检测)或FIFO。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 Would it be sensible to run this splashscreen and drive the LVDS logic with an external clock while continuously sampling the video pixel clock for activity, then switch to the video when the pixel clock is detected switch the outputs? If the input video pixel clock is not a constant clock source, then you clearly must provide an alternative clock. There are several design approaches which can work for the application you describe -- just pick one and forge ahead. Personally, I would not switch clock sources. I would provide a constant, fixed timebase for internal logic, and design a path for bridging the input video signal to the internal timebase. Typical implementations use either oversampling (and input pixel clock edge detection) or FIFOs. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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我最喜欢的恒定内部时钟方法是使用略高于最大输入像素时钟频率的频率。
然后在输入时钟和恒定时钟之间使用短FIFO(通常几乎为空)。 由于恒定时钟稍微快一些,如果始终在FIFO上启用写入和读取,则不会溢出,并且可以将非EMPTY条件用作FIFO下游的时钟使能或数据有效信号。 如果您的外部视频源可能会消失,您可能需要在检测到之后进入的视频时重置FIFO。 如果FIFO在外部源启动时由于时钟毛刺而变得“混乱”,这可能会有所帮助。 如果视频源本身有可用的时钟,我通常不赞成使用不相关的时钟进行过采样。 也可以使用FIFO的EMPTY输出来检测输入时钟频率。 在一段相当长的时间内计算非空循环可以为您提供合理准确的读数。 请注意,停止的输入时钟可以防止标志通过FIFO传播,但EMPTY标志是“保守的”,这意味着如果FIFO可能为空,只要您继续提供读时钟,该标志就会被置位。 因此,您还可以使用EMPTY循环计数检测缺少输入(频率小于某个阈值)。 - Gabor 以上来自于谷歌翻译 以下为原文 My favorite approach for a constant internal clock is to use a frequency that's slightly higher than the maximum input pixel clock rate. Then use a short FIFO (it will be normally almost empty) between the input clock and the constant clock. Since the constant clock is slightly faster, if you always enable both write and read on the FIFO you won't ever overflow and you can use the not EMPTY condition as a clock enable or data valid signal downstream of the FIFO. If your external video source can go away, you'll probably need to reset the FIFO when you detect the video coming in afterwards. That can help if the FIFO becomes "confused" due to clock glitches when the external source starts up. I generally frown upon using oversampling with an unrelated clock if there is a clock available from the video source itself. It's also possible to use the FIFO's EMPTY output to detect the incoming clock frequency. Counting non-empty cycles over some reasonably large time period can give you a reasonable accurate reading. Note that a stopped input clock can prevent flags from propagating through a FIFO, but the EMPTY flag is "conservative" meaning that if the FIFO could be empty the flag will be asserted as long as you continue to provide the read clock. Thus you can also detect lack of input using the EMPTY cycle count (frequency less than some threshold). -- Gabor |
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