请问什么是spartan3的默认驱动强度？

嗨，
您使用的是Xilinx MIG IP还是控制器？
驱动强度取决于您的IO标准，请参考Spartan-3 FPGA的selectIO用户指南，或者如果您实施设计而不添加驱动强度约束，我认为您可以在FPGA编辑器中看到它。
我不认为你需要50MHz的DCI。
请运行IBIS模拟以了解信号特征。
问候，
Vanitha。
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以下为原文

Hi,
 
Are you using Xilinx MIG IP or your controller?
 
The drive strength depends on your IO standard, please refer selectIO user guide for Spartan-3 FPGA or if you implement the design with out adding the drive strength constraint I think you can see it in FPGA editor.
I do not think you need  DCI for 50MHz.
 
Please run IBIS simulations to know the signal characteristics.
 
Regards,
Vanitha.
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你好
您可以在以下链接中找到与此主题相关的更多信息，您可以根据这些链接调整驱动器强度值
http://forums.xilinx.com/t5/General-Technical-Discussion/How-can-I-know-whether-drive-strength-is-enough/td-p/290235
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/the-impact-of-the-drive-strength-on-the-rise-time/td-p/343071
问候，
Vanitha。
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以下为原文

Hi
 
You can find more info related to this topic in below links  based on which you can tweak your drive strength value
 
http://forums.xilinx.com/t5/General-Technical-Discussion/How-can-I-know-whether-drive-strength-is-enough/td-p/290235
 
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/the-impact-of-the-drive-strength-on-the-rise-time/td-p/343071
 
 
 
Regards,
Vanitha.
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PCB设计中可能存在一些信号完整性问题（尤其是阻抗不匹配）。
如果您不使用DCI，您可能需要终止。
请参阅用户指南（两个Xilinx SDRAM）推荐
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以下为原文

There could be some Signal Integrity problem (especially impedance mismatching) in PCB design.
 
If you do not use DCI you may need terminations .
 
Please folow the user guides(Both Xilinx SDRAM)  recomendations
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我为sdram dq busin ucf设置了drive = 8ma，并发现信号有过冲，这可能是我的电路板问题的原因。
我敢打赌，当在信号轨迹的不同点探测信号时，你会看到过冲幅度的差异。
重要的波形是负载引脚上的波形，而不是信号驱动器或两者之间的任何点。
此外，您的示波器探头可能很有助于超调的*外观*。
如果在弯曲或松开示波器探头引线时波形形状发生变化，这表明您的测量技术会影响测量。
如果我没有在ucf中指定任何驱动器，那么默认驱动器强度是多少？
从一个设计师到另一个设计师，请不要依赖默认的驱动强度。
为所有IO引脚明确分配驱动强度和边沿速率。
另外，请记住，驱动强度（和输出阻抗）的容差变化很大，可达-50％到+ 100％。
请注意，没有使用DCI作为没有足够的引脚，我的sdram运行在~50Mhz，我觉得DCI是没有必要的。
请注意，时钟信号的信号完整性问题对工作频率完全不敏感。
错误的时钟边沿或双时钟将导致您的设计在*任何*时钟频率下失败。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

I set the drive = 8ma for sdram dq bus in ucf, and find there is overshoot on the signal, which may be the cause of my board issue.
 
I would wager that you will see differences in overshoot amplitude when probing the signal at different points in the signal trace.  The waveform which matters is the waveform at the load pin(s), not the signal driver or any point in between the two.
 
Also, your scope probe may very well be contributing to the *appearance* of overshoot.  If the waveform shape changes when you curl or uncurl the scope probe leads, this is a good sign that your measurement technique can affect the measurements.
 
what's the default drive strength if I don't specified any drive in ucf?
 
From one designer to another, please do not rely on default drive strength.  Assign drive strength and edge rate explicitly for all IO pins.  Also, keep in mind that tolerances on drive strength (and output impedance) are widely variable, as much as -50% to +100%.
 
note there is no DCI used as no enough pins and my sdram runs at ~50Mhz, under which I think DCI is not necessary.
 
Please note that signal integrity problems with clock signals are entirely insensitive to operating frequency.  A false clock edge, or double-clocking, will cause your design to fail at *any* clock frequency.
 
-- Bob Elkind
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