像往常一样，当我组织思考并寻求帮助时，我偶然发现了一个解决方案。
首先，我在EDK创建的MHS文件中手动添加了“C_MCB_USE_EXTERNAL_PLL”。
然后我发现从MPMC v6.04a指南中阅读以下内容后，我的时钟共享连接不正确。
设计已成功通过Mapping，并在P＆amp; R。
（http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_04_a/mpmc.pdf）：
当两个MPMC位于设备的同一侧时，它们必须都在相同的存储器时钟上运行。以下是微处理器硬件规范（MHS）文件示例，说明当两个MPMC位于其上时两个MPMC如何使用级联时钟连接。
该装置的同一侧：BEGIN mpmcPARAMETER INSTANCE = MPMC_0 ... PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_oPORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_oPORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_oPORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_oPORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_oENDBEGIN mpmcPARAMETER INSTANCE = MPMC_1PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1 ... PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_oPORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_oPORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_oPORT
MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_oPORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_oEND
在原帖中查看解决方案
以上来自于谷歌翻译
以下为原文
As usual as soon as I organize thoughts and ask for help I stumble across a solution.
First, I added the "C_MCB_USE_EXTERNAL_PLL" manually in the MHS file created by the EDK. Then I discovered that my clock sharing was wired incorrectly after reading the following from the MPMC v6.04a guide. Design has successfully passed Mapping and is in P&R.
(http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_04_a/mpmc.pdf):
When two MPMCs are located on the same side of the device, they must both operate on the same memory clock.
The following is an Microprocessor Hardware Specification (MHS) file example of how the two MPMCs use
cascaded clock connections when they are both located on the same side of the device:
BEGIN mpmc
PARAMETER INSTANCE = MPMC_0
...
PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_o
PORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_o
PORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_o
PORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_o
PORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_o
END
BEGIN mpmc
PARAMETER INSTANCE = MPMC_1
PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1
...
PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_o
PORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_o
PORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_o
PORT MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_o
PORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_o
END
View solution in original post
像往常一样，当我组织思考并寻求帮助时，我偶然发现了一个解决方案。
首先，我在EDK创建的MHS文件中手动添加了“C_MCB_USE_EXTERNAL_PLL”。
然后我发现从MPMC v6.04a指南中阅读以下内容后，我的时钟共享连接不正确。
设计已成功通过Mapping，并在P＆amp; R。
（http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_04_a/mpmc.pdf）：
当两个MPMC位于设备的同一侧时，它们必须都在相同的存储器时钟上运行。以下是微处理器硬件规范（MHS）文件示例，说明当两个MPMC位于其上时两个MPMC如何使用级联时钟连接。
该装置的同一侧：BEGIN mpmcPARAMETER INSTANCE = MPMC_0 ... PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_oPORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_oPORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_oPORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_oPORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_oENDBEGIN mpmcPARAMETER INSTANCE = MPMC_1PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1 ... PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_oPORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_oPORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_oPORT
MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_oPORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_oEND
在原帖中查看解决方案
以上来自于谷歌翻译
以下为原文
As usual as soon as I organize thoughts and ask for help I stumble across a solution.
First, I added the "C_MCB_USE_EXTERNAL_PLL" manually in the MHS file created by the EDK. Then I discovered that my clock sharing was wired incorrectly after reading the following from the MPMC v6.04a guide. Design has successfully passed Mapping and is in P&R.
(http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_04_a/mpmc.pdf):
When two MPMCs are located on the same side of the device, they must both operate on the same memory clock.
The following is an Microprocessor Hardware Specification (MHS) file example of how the two MPMCs use
cascaded clock connections when they are both located on the same side of the device:
BEGIN mpmc
PARAMETER INSTANCE = MPMC_0
...
PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_o
PORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_o
PORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_o
PORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_o
PORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_o
END
BEGIN mpmc
PARAMETER INSTANCE = MPMC_1
PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1
...
PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_o
PORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_o
PORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_o
PORT MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_o
PORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_o
END
View solution in original post
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