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[问答]

无法在IOS 11上使用时钟向导实例化dcm

我无法使用ISE 11上的Clocking Wizard实现dcm。当使用Verilog实现设计时,它会产生以下错误:
错误:ConstraintSystem:59  - 约束[dcm_10Mhz_arwz.ucf(4)]:未找到INST“DCM_SP_INST”。
请验证:1。指定的设计元素实际存在于原始设计中。
2.指定的对象在约束源文件中拼写正确。
所有错误都属于同一类型。
好吗,拜托?
谢谢!

以上来自于谷歌翻译


以下为原文

I can't instatiate dcm using Clocking Wizard on ISE 11. When implementing design using Verilog, it gives several errors like:

ERROR:ConstraintSystem:59 - Constraint
   [dcm_10Mhz_arwz.ucf(4)]: INST "DCM_SP_INST" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

All errors are of the same type.

Any idea, please?

Thank you!

回帖(1)

杨玲

2019-5-27 12:41:37
看起来您已经附加了体系结构生成的.ucf文件
向导到你的项目。
实例名称“DCM_SP_INST”来自
实例化的模块。
因此,您需要编辑要包含的.ucf文件
该模块的分层路径。
例如,如果您实例化了
您的顶级模块:
dcm_10Mhz foo

...
);
然后你需要改变:
INST DCM_SP_INST CLK_FEEDBACK = 1X;
至:
INST foo / DCM_SP_INST CLK_FEEDBACK = 1X;
或者你可以不像我想的那样包含这个.ucf文件
除了可能的周期限制之外的所有事情
在源文件中。
HTH,
的Gabor
-  Gabor

以上来自于谷歌翻译


以下为原文

It looks like you have attached the .ucf file generated by the architecture
wizard to your project.  The instance name "DCM_SP_INST" comes from
the instantiated module.  So you would need to edit the .ucf file to contain
the hierarchical path to that module.  For example if you instantiated the
module from your top level as:
 
dcm_10Mhz foo
(
 ...
);
 
Then you need to change:
 
INST DCM_SP_INST CLK_FEEDBACK = 1X;
 
to:
 
INST foo/DCM_SP_INST CLK_FEEDBACK = 1X;
 
Alternately you can just not include this .ucf file as I would think
everything except possibly period constraints would already be
in the source file.
 
HTH,
Gabor
-- Gabor
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