现在我发现的唯一解决方案是在设计中反转该时钟（clk_inverted 以下为原文
Right now the only solution that I found is to invert that clock inside the design (clk_inverted<= not clk) and to use "if rising_edge(clk_inverted)"...but there must be a simpler solution..
您好，不完全是您的问题的答案，但我很好奇您为什么要这样做？
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以下为原文
Hello,
Not exactly an answer to your question, but I'm curious why you would want to do that?www.xilinx.com
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www.xilinx.com
以上来自于谷歌翻译
以下为原文
Hello,
Not exactly an answer to your question, but I'm curious why you would want to do that?www.xilinx.com
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因为在我的设计中，我使用时钟的下降沿来采样外部生成的一些数据（在同一时钟的上升沿）。
这是我必须满足的项目要求。
要做到这一点，使用指令“if falling_edge（clk）”与反转时钟并使用“if rising_edge（clk_inverted）”相比更为简单。
但是如果我使用“if falling_edge（clk）”那么我就没有任何选择来选择ILA上的时钟下降沿。
以下为原文
Because in my design I am using the falling edge of a clock to sample some data generated externally (on the rising edge of the same clock). This is a project requirement that I have to fullfill. To do this it is simpler to use the directive "if falling_edge(clk) " compared to inverting the clock and use "if rising_edge(clk_inverted)". But if I use "if falling_edge(clk) " then I do not have any options to select the falling edge of the clock on the ILA.
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这是我必须满足的项目要求。
要做到这一点，使用指令“if falling_edge（clk）”与反转时钟并使用“if rising_edge（clk_inverted）”相比更为简单。
但是如果我使用“if falling_edge（clk）”那么我就没有任何选择来选择ILA上的时钟下降沿。
以上来自于谷歌翻译
以下为原文
Because in my design I am using the falling edge of a clock to sample some data generated externally (on the rising edge of the same clock). This is a project requirement that I have to fullfill. To do this it is simpler to use the directive "if falling_edge(clk) " compared to inverting the clock and use "if rising_edge(clk_inverted)". But if I use "if falling_edge(clk) " then I do not have any options to select the falling edge of the clock on the ILA.
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啊，我明白了。
如果您刚刚定义了clk_inverted并选择它作为ILA的时钟并且仍然在逻辑的其余部分使用falling_edge（clk），该怎么办？
www.xilinx.com
以下为原文
Ah I see.
What if you just defined clk_inverted and selected it as the clock for the ILA and still use falling_edge(clk) in the rest of your logic?
www.xilinx.com
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如果您刚刚定义了clk_inverted并选择它作为ILA的时钟并且仍然在逻辑的其余部分使用falling_edge（clk），该怎么办？
www.xilinx.com
以上来自于谷歌翻译
以下为原文
Ah I see.
What if you just defined clk_inverted and selected it as the clock for the ILA and still use falling_edge(clk) in the rest of your logic?
www.xilinx.com
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