VC707主板上使用Vivado 2015.4中的ILA内核时，有时它被硬件管理员识别，有时不被识别，请问如何解决？

乔： 
我一直在试验ILA核心，看看哪些有效，哪些无效。
仅通过观察，将超过80个信号连接到ILA将导致其无法工作。
ILA的时钟来自DCM，它为我的大部分逻辑和内核产生全局时钟。
我向ILA添加了两个pipleline阶段，但我遇到了与以前相同的80信号限制。
我还注意到，如果ILA无法正常运行，有时候整个FPGA都会停止工作。
当我的MicroBlaze处理器仅打印出“欢迎”屏幕的第一行时，我可以看到这一点 
如果我发现更多信息，我会将其发布到此主题。
B.T.W  - 感谢所有试图提供帮助的人。
欢迎您的建议，非常感谢。
在原帖中查看解决方案



以下为原文

Joe:
 
     I've been experimenting with the ILA core to see what works and what doesn't.  Just by observation, connecting more than 80 signals to the ILA will cause it to not work.  The clock to the ILA is from a DCM that produces a global clock to most of my logic and cores.  I added two pipleline stages to the ILA but I ran into the same 80 signal limit as before.  I've also noticed that if the ILA fails to function properly, sometimes, the entire FPGA stops working.  I can see this when my MicroBlaze processor will print out only the first line of my 'Welcome' screen
 
     If I find out more information I will post it to this thread.
 
B.T.W - Thanks to everyone who has tried to help.  Your suggestions are welcome and much appreciated.
View solution in original post

为什么你认为这与torouting有什么关系？



以下为原文

Why do you think this has anything to do with routing?

我的FPGA使用了很多内核。
我正在使用MicroBlaze，DDR3控制器，Aurora核心，CoaXPress核心和接口逻辑以可用的方式连接核心。 
在开始工作的过程中，我开始只使用CoaXPress核心的Verilog模型，ILA运行良好。 
我添加了DDR3控制器，一切正常。
数据按预期流入/流出DDR3内存。 
我添加了Aurora核心来完成整个数据路径，ILA一直失败。
ILA内核未被识别为位于JTAG链上或已被识别但硬件管理器给我错误。 
在不改变FPGA内的任何逻辑的情况下，我开始删除与ILA的连接。
当我得到大约80个信号时，ILA开始正常工作。
时间报告没有列出任何与ILA相关的信号的时间违规（我可以说）。



以下为原文

     My FPGA uses a lot of cores.  I'm using a MicroBlaze, DDR3 Controller, Aurora core, a CoaXPress core and interface logic to connect the cores in a usable way. 
 
    In the process of getting things to work I started out with just my a Verilog model of the CoaXPress core, The ILA worked fine.
 
    I added the DDR3 controller, everything worked fine.  Data was flowing in/out of DDR3 memory as expected.
 
    I added the Aurora core to complete the entire data path and the ILA failed consistently.  Either the ILA core is not recognized as being on the JTAG chain or it is recognized but the Hardware Manager gives me errors.
 
    Without changing any logic within the FPGA, I started to remove connections to the ILA.  When I got down to about 80 signals the ILA started to work properly.  The timing report didn't list any timing violation on signals that related to the ILA (that I could tell).

您是否尝试过增加ILA中的管道/同步阶段？
我有ILA的问题，通常Vivado需要重启，或者有时我必须重新创建ILA本身。
偶尔遇到JTAG频率问题。
如果你的时机已经过去，我不知道为什么你会认为路由存在问题，除非有一些不受约束的路径。



以下为原文

Did you try increasing the pipeline/ synchronization stage in the ILA?
 
I've had issues with ILA where it is usually Vivado which needs a restart or sometimes I have to recreate the ILA itself. Have occasionally run into issues with JTAG frequency. If your timing is passing I don't know why you would think there is an issue with the routing unless there are some unconstrained paths.

只是一个猜测......
我曾经在ISE中遇到这个问题，只要ILA时钟在本地网络而不是时钟网络上路由就会发生。
我从来没有遇到Vivado的问题，但也许在这里发生了相同的时钟路由问题。
---
乔萨姆森



以下为原文

Just a guess...
I used to have this problem in ISE, and it happened whenever the ILA clock was routed on a local net rather than a clock net. I've never had a problem with Vivado, but maybe the same clock routing problem is happening here.
 
 
---
Joe Samson

乔： 
我一直在试验ILA核心，看看哪些有效，哪些无效。
仅通过观察，将超过80个信号连接到ILA将导致其无法工作。
ILA的时钟来自DCM，它为我的大部分逻辑和内核产生全局时钟。
我向ILA添加了两个pipleline阶段，但我遇到了与以前相同的80信号限制。
我还注意到，如果ILA无法正常运行，有时候整个FPGA都会停止工作。
当我的MicroBlaze处理器仅打印出“欢迎”屏幕的第一行时，我可以看到这一点 
如果我发现更多信息，我会将其发布到此主题。
B.T.W  - 感谢所有试图提供帮助的人。
欢迎您的建议，非常感谢。



以下为原文

Joe:
 
     I've been experimenting with the ILA core to see what works and what doesn't.  Just by observation, connecting more than 80 signals to the ILA will cause it to not work.  The clock to the ILA is from a DCM that produces a global clock to most of my logic and cores.  I added two pipleline stages to the ILA but I ran into the same 80 signal limit as before.  I've also noticed that if the ILA fails to function properly, sometimes, the entire FPGA stops working.  I can see this when my MicroBlaze processor will print out only the first line of my 'Welcome' screen
 
     If I find out more information I will post it to this thread.
 
B.T.W - Thanks to everyone who has tried to help.  Your suggestions are welcome and much appreciated.