怎么在verilog中实现一个相当大的LUT

谢谢
有趣，
我是否理解LUT你的意思是RAM块， 
并使用它们作为查找表来进行失真，
您可以使用外部文件直接加载RAM 
这可能会给你一些指示，
https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Initializing-Block-RAM-with-External-Data-File/td-p/229193
外部加载RAMS在PicoBlaze项目中经常使用，允许人们更改RAM中的代码而无需完全重新编译FPGA，
玩得开心，让我们知道它是怎么回事，
在原帖中查看解决方案



以下为原文

Thank you
 
interesting,
 
Do I understand then by LUT your meaning the RAM blocks,
    and your using them as a Look Up Table to do the distortion ,
 
You can use an external file to load RAMs directly 
    this might give you a few pointers,
 
https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Initializing-Block-RAM-with-External-Data-File/td-p/229193
 
Loading RAMS externally is  used a lot in the PicoBlaze project, allows one to change the code in the ram without having to re compile the FPGA completely,
 
Have fun and let us know how it goes,
 
View solution in original post

嗨，
实现此目的的一种方法如下：不使用LUT值生成CSV，您可以生成Verilog文件。
像这样的东西：
初始开始：my_lut_vals
lut_val [0] ='h11223344
lut_val [1] ='h55667788
...
结束
然后将该文件包含在实例化LUT的位置。
reg [31：0] lut_vals [1：N];`include“my_lut_vals.vh”
谢谢，
叶夫根



以下为原文

Hi,
 
One way to implement this is as follows. Instead of generating CSV with the LUT values, you can generate Verilog file. Something like that: 
 
initial begin: my_lut_valslut_val[0] = 'h11223344lut_val[1] = 'h55667788...endThen include that file in place you instantiate the LUT.
 
reg [31:0] lut_vals [1:N];
`include "my_lut_vals.vh"Thanks,
Evgeni
 
 

我可以问，为了您自己的知识，为什么要在MATLAB中实现逻辑值？



以下为原文

Can I ask , for my own knowledge why you want to implement the logic values in MATLAB ?
 
 

我正在制作一个驱动程序，我想对数据实现复杂的数字预失真。
我可以使用Matlab生成过滤器等，然后将结果加载到LUT中。
这减轻了执行计算密集型工作的电路的负担。



以下为原文

I am making a driver, and I want to implement complex digital predistortion to the data. I can use Matlab to generate filters and such and then load the results into a LUT. This takes the burden off of circuitry doing computationally intensive work.