LUT实现的逆变器真的是FPGA上的逆变器吗？

LUT1_1原语将在LUT4和LUT6中实现，具体取决于器件系列。
正如名称LUT（查找表）所示，它是一个16：1（LUT4）或64：1（LUT6）存储器，逻辑输入作为地址。
LUT可以通过查找存储器来生成输出，通过4个输入（LUT4）或6个输入（LUT6）处理任意逻辑功能。
jamesjisun写道：
你好，
当我在原理图视图中单击LUT时，它会按预期显示逆变器。
但我想知道它是通过逆变器在Xilinx FPGA上实现还是实际上原理图不等同于FPGA的真相？
谢谢，
Ĵ
干杯，吉姆
在原帖中查看解决方案



以下为原文

The LUT1_1 primitive will be implemented in a LUT4 and LUT6 depending on the device family. As the name LUT (look up table) indicates, it is a 16-to-1 (LUT4) or 64-to-1 (LUT6) memory with the logic inputs as the address. LUT can handle any arbitrary logic function with 4 inputs (LUT4) or 6 inputs (LUT6) by way of looking up the memory to generate the output.

jamesjisun wrote:
Hi there,
 
When I click an LUT in the schematic view and it shows an inverter as expected. But I am wondering if it is implemented on Xilinx FPGA by an inverter or actually the schematic view is not equivalent to the truth on the FPGA?
 
Thanks,
J

Cheers,
JimView solution in original post

不，它可能是使用FPGA上的LUT实现的。
通常最好不要在原始数字逻辑门方面考虑FPGA设计！



以下为原文

No, it will probably be implemented using a LUT on the FPGA. It's generally best not to think of FPGA designs in terms of primitive digital logic gates!

不，它[逆变器]可能会使用FPGA上的LUT实现。
同意，但并非总是如此。
例如，时钟极性选择通常是掩埋在较大基元内的多路复用器或反相器。
通常最好不要在原始数字逻辑门方面考虑FPGA设计！
同意。
听起来像是一个学术研究项目（参见另一个最近想要比较长线和短线的线程）。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

No, it [inverter] will probably be implemented using a LUT on the FPGA.
 
Agreed, but not always.  For instance, clock polarity selects are often muxes or inverters buried within a larger primitive.
 
It's generally best not to think of FPGA designs in terms of primitive digital logic gates!
 
Agreed.  Sounds like an academic study project (see another recent thread wanting to compare long lines vs. short lines).
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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同意，但并非总是如此。
例如，时钟极性选择通常是掩埋在较大基元内的多路复用器或反相器。
是的，我想补充一点，但后来我认为选择是可编程的，所以如果你眯着眼睛它仍然有点像查找表。
我同意在这些情况下，潜在的实施可能会明显更多。



以下为原文

Agreed, but not always.  For instance, clock polarity selects are often muxes or inverters buried within a larger primitive.

Yeah, I was going to add that caveat, but then I thought that the selection is programmable, so if you squint it's still a bit like a lookup table. I agree that the underlying implementation would probably be decidedly more invertery in these cases.
 

是的，我想补充一点，但后来我认为选择是可编程的，所以如果你眯着眼睛它仍然有点像查找表。
我同意在这些情况下，潜在的实施可能会明显更多。
由于这种查询很可能是一篇学术论文，所以只需要对整个FPGA进行设备级描述即可。
我们可以算上分钟，直到Austin Lesea来救援。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Yeah, I was going to add that caveat, but then I thought that the selection is programmable, so if you squint it's still a bit like a lookup table. I agree that the underlying implementation would probably be decidedly more invertery in these cases.
 
As this inquiry is most likely for an academic paper, nothing less than a device-level description of the entire FPGA will suffice.  We can count the minutes until Austin Lesea comes to the rescue.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我发现了一些关于如何实现可选择的逆变器的很好的信息 - 也许这些信息类似于时钟极性选择所使用的信号。



以下为原文

I found some great information on how selectable inverters are implemented - perhaps these are similar to the ones used by clock polarity selects.

嗨，
感谢你们双方的回答。
我认为LUT只是一个名字，它应该由几个门构成。
我很困惑，如果一个简单的逆变器就足够了，LUT应该缩小成一个逆变器，而不是一个复杂的组合逻辑。
这也是电力问题。
关于LUT如何组成的任何想法？
干杯，
Ĵ



以下为原文

Hi,
 
Thanks for the answers from both of you. I think LUT is just a name, and it should be consisted of several gates. And I am confusing if a simple inverter is enough, the LUT should shrink to be an inverter instead of a complicated combinational logic. This is also from the power issue.
 
Any idea on how a LUT is composed of?
 
Cheers,
J

LUT本质上是一个具有许多输入和输出的存储器，由一整堆门组成。
例如，阅读Spartan-6 CLB用户指南。
这些都是硬件固定的。
正是它们的可重配置性使它们能够模拟逆变器和其他门。
LUT可能在“功能上”减少到逆变器，但底层实现不能改变。



以下为原文

A LUT is essentially a bit of memory with a number of inputs and outputs and consists of a whole stack of gates. Have a read of, for example, the Spartan-6 CLB User Guide.
 
These are fixed in hardware. It is their reconfigurability that allows them to emulate inverters and other gates. The LUT might 'functionally' reduce to an inverter, but the underlying implementation can't be changed.
 
 
 

LUT1_1原语将在LUT4和LUT6中实现，具体取决于器件系列。
正如名称LUT（查找表）所示，它是一个16：1（LUT4）或64：1（LUT6）存储器，逻辑输入作为地址。
LUT可以通过查找存储器来生成输出，通过4个输入（LUT4）或6个输入（LUT6）处理任意逻辑功能。
jamesjisun写道：
你好，
当我在原理图视图中单击LUT时，它会按预期显示逆变器。
但我想知道它是通过逆变器在Xilinx FPGA上实现还是实际上原理图不等同于FPGA的真相？
谢谢，
Ĵ
干杯，吉姆



以下为原文

The LUT1_1 primitive will be implemented in a LUT4 and LUT6 depending on the device family. As the name LUT (look up table) indicates, it is a 16-to-1 (LUT4) or 64-to-1 (LUT6) memory with the logic inputs as the address. LUT can handle any arbitrary logic function with 4 inputs (LUT4) or 6 inputs (LUT6) by way of looking up the memory to generate the output.

jamesjisun wrote:
Hi there,
 
When I click an LUT in the schematic view and it shows an inverter as expected. But I am wondering if it is implemented on Xilinx FPGA by an inverter or actually the schematic view is not equivalent to the truth on the FPGA?
 
Thanks,
J

Cheers,
Jim