如果我们使用约束2，“VALID ns AFTER ...”部分为X添加什么值？

我重新阅读你的帖子两次，我的头仍在旋转;-)
偏移输入和输出约束都与FPGA的引脚有关。
任何内部路径（在FPGA内）都由工具计算。
因此，您需要告诉工具的是FPGA输入端的实际可用设置和保持时间。
例如，假设您有一个设备，其时钟信号与FPGA的时钟输入相同。
您需要找到外部设备在时钟之后更改其输出所需的最短和最长时间。
假设外部器件的时钟到达时间与FPGA引脚的时钟到达时间相同，则输出时间的最小时钟将是可用的保持时间。
时钟周期减去最大时钟到输出时间将是FPGA可用的建立时间。
现在，约束计算为设置时间和有效时间，而不是设置和保持。
有效时间是可用设置和保持时间的总和。
请注意，由于板级时钟路径差异，其中一个可能是负的。
假设您的外部器件的Q最大时钟为3.8 ns，Q的最小时钟为0.6 ns，时钟网络的布线使得外部器件和FPGA同时看到时钟上升沿。
然后忽略电路板布线延迟，8 ns周期时钟的建立时间为8  -  3.8或4.2 ns，保持时间为0.6 ns。
因此有效时间为4.2 + 0.6 = 4.8 ns，约束如下：
OFFSET = IN 4.2 ns有效4.8 ns在CLK上升之前;
我附上的图片显示了一些不同的设置和保持时间，但这给出了这个想法。
-  Gabor



以下为原文

I re-read your post twice and my head is still spinning ;-)
 
Offset in and out constraints are all with respect to the pins of the FPGA.  Any internal paths (within the FPGA) are computed by the tools.  So what you need to tell the tools is the actual available setup and hold time at the FPGA pins for inputs.  For example, lets say you have a device clocked with the same clock signal provided to the clock input of the FPGA.  You need to find the minimum and maximum time that the external device can take to change it's outputs after the clock.  Assuming that the clock arrival time to the external device is the same as the clock arrival at the pin of the FPGA, then the minimum clock to output time will be the available hold time.  The clock period minus the maximum clock to output time will be the setup time available to the FPGA.  Now the constraint is calculated as setup time and valid time rather than setup and hold.  Valid time is the sum of available setup and hold times.  Note that due to board level clock path differences it is possible for one of these to be negative.  Let's say that your external device has a max clock to Q of 3.8 ns, a minimum clock to Q of 0.6 ns, and the clock net is routed such that the external device and the FPGA see the rising clock edge at the same time.  Then ignoring board routing delays for the moment, the setup time for you 8 ns period clock would be 8 - 3.8 or 4.2 ns, and the hold time would be 0.6 ns.  So the valid time would be 4.2 + 0.6 = 4.8 ns, and the constraint would look like:
 
OFFSET = IN 4.2 ns VALID 4.8 ns BEFORE CLK RISING ;
 
I'm attaching a picture showing some different setup and hold times, but which gives the idea.
-- Gabor

的Gabor，
让我知道为什么我的帖子让你旋转:)
作为约束的偏移，我认为我们在同一页面上，我们只是以不同的方式看待它...这就是为什么 -
你说 - 如果我的clk周期是8ns并且外部设备的最大clk-q延迟是3.8ns，那么可用的设置时间是8  -  3.8ns = 4.2ns。
这几乎和我说的一样 - “我的clk周期是8ns，路由延迟是xyz ns，然后FPGA可以将信号从i / p引脚路由到FF = 8  -  xyz ns”。
如果我们从你的例子中包括最大clk-q延迟为3.8ns，那么可用的建立时间将是= 8  - （xyz + 3.8）ns
现在，根据我的理解 - 这8  - （xyz + 3.8）ns必须超过FPGA架构中FF的Tsetup。
如果
8  - （xyz + 3.8）> FPGA中的FF的Tsetup，然后该工具将给出时序违规，即因为输入路径很长，当输入数据到达FF时，数据在设置窗口内转换
clk边缘 - 因此失败。
如果我们在同一页面上，请告诉我......？
我的问题是 - 在CLK上升之前使用-OFFSET = IN 4.2 ns VALID 4.8 ns之间是否有任何特别的优势;
VsOFFSET =在CLK上升之前4.2 ns;？
此外，我的外部设备（生成输入数据和clk）进入FPGA  - 也是一个FPGA。
那么我应该看一下数据表中的哪个部分来获得FPGA的clk-q延迟（我看到几个clk-q字段）？
对于抵消，我上面的帖子上的任何输入？
ž。



以下为原文

gabor,
 
do let me know why my post made your head spin :)
 
as the the offset in constraint, i think we are on the same page, we're just looking at it differently ... here's why -
 
you say - if my clk period is 8ns and max clk-q delay of external device is 3.8ns, then setup time available is 8 - 3.8ns = 4.2ns.
 
this is almost the same as if i say - "my clk period is 8ns, the routing delay is xyz ns, then the amount of time available for FPGA to route signal from i/p pin to FF = 8 - xyz ns".
if we include the max clk-q delay of 3.8ns from your example, then the setup time available would be = 8 - (xyz + 3.8) ns 
 
now, as per my understanding - this 8 - (xyz + 3.8) ns has to be more than the Tsetup of the FF in the FPGA fabric. if 
8 - (xyz + 3.8) > Tsetup of the FF in the FPGA, then the tool will give a timing violation i.e. because input path is very long, by the time the input data reaches the FF, the data is transitioning inside the setup window of the clk edge - hence a failure.
 
let me know if we're on the same page here ... ?
 
my question is - is there any particular advantage between using - OFFSET = IN 4.2 ns VALID 4.8 ns BEFORE CLK RISING ; Vs OFFSET = IN 4.2 ns BEFORE CLK RISING ;?
 
Also, my external device (which is generating the input data and clk) going into the FPGA - is ALSO an FPGA.
so which section in the datasheet should I look at to get any time of clk-q delay for the FPGAs (i see several clk-q fields)?
 
also, for offset out, any inputs on that from my above post?
 
z.

并且......要添加到我的问题列表中 - 我们是将偏移输入/偏移输出仅应用于数据引脚还是从FPGA输入/输出的clk引脚？



以下为原文

and ... to add to my list of questions - do we apply offset in/offset out to only the data pins or also the clk pins going in/out from the FPGA?

“现在，根据我的理解 - 这8  - （xyz + 3.8）ns必须超过FPGA架构中FF的Tsetup。
8  - （xyz + 3.8）> FPGA中的FF的Tsetup，然后该工具将给出时序违规，即因为输入路径很长，当输入数据到达FF时，数据在设置窗口内转换
clk边缘 - 因此失败。
“
我认为正确的说法是：
如果8  - （xyz + 3.8）小于FPGA中FF的Tsetup，则该工具将给出时序违规，即因为输入路径非常长，当输入数据到达FF时，数据正在内部转换
clk边缘的设置窗口 - 因此失败。
但请记住，实际的Tsetup是通过从引脚（时钟和数据）到触发器的内部路由计算出来的。
如果您的FF锁定在IOB中，那么工具无法尝试改善设置或保持时间，它们只能报告实际的松弛（如果失败则为负）。
如果FF位于结构中，则工具可以使用路由延迟来修复某些类型的设置或保留问题。
默认综合设置“自动”允许工具根据时序要求决定FF应该在结构中还是IOB中。
“我的问题是 - 在CLK上升之前使用-OFFSET = IN 4.2 ns VALID 4.8 ns之间是否有任何特别的优势;在CLK上升之前VsOFFSET = IN 4.2 ns之间有什么特别的优势;？”
如果没有约束的VALID部分，工具将仅检查设置时间。
我不记得这些工具是否完全忽略了保持时间或者假设它为零。
在任何情况下，最好指出实际可用的保持时间，以便工具可以更好地决定FF放置和相关时间。
“此外，我的外部设备（生成输入数据和clk）进入FPGA  - 也是一个FPGA。
那么我应该看一下数据表中的哪个部分来获得FPGA的clk-q延迟时间（我看到几个clk-q字段）？“
如果另一个器件是Xilinx FPGA，那么通常您可以从最后一个P＆amp; R时序报告的“数据表”部分获得此信息。
请注意，如果FPGA提供时钟和数据，则需要将包括时钟转发ODDR的所有输出FFS锁定到IOB中。
在论坛中搜索“source synchronous”以获取有关在此配置中进行稳健输出计时的更多信息。
如果您的数据输出“单数据速率”并且您在时钟上升沿接收数据，则标准做法是将ODDR用作反相时钟转发器，方法是将上升沿D连接到“0”并且下降 -
边D到'1'。
这将上升时钟边沿置于数据位周期的中心。
OFFSET OUT约束后，从FPGA引脚的时钟输入到FPGA引脚的数据输出有一个最大延迟。
如果将输出FF放在IOB中，除了告诉您设计是否满足时序外，它实际上什么都不做 - 它不能改变时钟输出时序。
如果您的输出FF在FPGA架构中或不受约束，那么这些工具有一些余地来尝试修复输出时序。
没有OFFSET OUT约束可以对输出延迟施加最小时钟。
这就是为什么你需要仔细地将所有输出放在IOB中以获得源同步设计的可用输出时序，其中FPGA驱动时钟和数据。
-  Gabor



以下为原文

"now, as per my understanding - this 8 - (xyz + 3.8) ns has to be more than the Tsetup of the FF in the FPGA fabric. if 
8 - (xyz + 3.8) > Tsetup of the FF in the FPGA, then the tool will give a timing violation i.e. because input path is very long, by the time the input data reaches the FF, the data is transitioning inside the setup window of the clk edge - hence a failure. "
 
I think the correct way to say thie is:
 
if  8 - (xyz + 3.8) is less than Tsetup of the FF in the FPGA, then the tool will give a timing violation i.e. because input path is very long, by the time the input data reaches the FF, the data is transitioning inside the setup window of the clk edge - hence a failure.
 
Remember however that the actual Tsetup is calculated with the internal routing from the pins (clock and data) to the flip-flop already taken into account.  If your FF is locked into the IOB, then there is nothing the tools can do to try to improve setup or hold time, they can only report the actual slack (negative if failing).  If the FF is in the fabric, the tools can use routing delays to fix some kinds of setup or hold issues.  The default synthesis setting of "Auto" allows the tools to decide whether the FF should be in the fabric or the IOB based on timing requirements.
 
"my question is - is there any particular advantage between using - OFFSET = IN 4.2 ns VALID 4.8 ns BEFORE CLK RISING ; Vs OFFSET = IN 4.2 ns BEFORE CLK RISING ;?"
 
Without the VALID part of the constraint, the tools will only check for setup time.  I don't remember if the tools totally ignore hold time or assume it to be zero.  In any case it is better to indicate the actual available hold time so the tools can make a better decision about FF placement and related timing.
 
"Also, my external device (which is generating the input data and clk) going into the FPGA - is ALSO an FPGA.
so which section in the datasheet should I look at to get any time of clk-q delay for the FPGAs (i see several clk-q fields)?"
 
If the other device is a Xilinx FPGA, then normally you get this information from the "datasheet" section of the final post P&R timing report.  Note that if the FPGA is sourcing the clock as well as the data, you need to lock all output FFS including the clock-forwarding ODDR into the IOBs.  Search the forums for "source synchronous" to get more information about making robust output timing in this configuration.  If your data is going out "single data rate" and you receive it on the rising clock edge, the standard practice is to use the ODDR as an inverting clock-forwarder by tying the rising-edge D to '0' and the falling-edge D to '1'.  This places the rising clock edge in the center of the data bit period.
 
OFFSET OUT AFTER constraints place a maximum delay from the clock input at the FPGA pin to the data output at the FPGA pin.  If you place your output FFs in the IOB, it really doesn't do anything except tell you whether the design met timing - it can't change the clock to output timing.  If your output FFs are in the FPGA fabric or unconstrained, the tools have some leeway to try to fix output timing.  There is no OFFSET OUT constraint that can impose a minimum clock to output delay.  That's why you need to carefully place all outputs in the IOBs to get a usable output timing for source-synchronous designs, where the FPGA drives both clock and data.
-- Gabor