如何使用ucf约束文件为输入数据添加一个小延迟？

您可以对UCF约束做的唯一事情是定义有效窗口（建立和保持时间）并查看工具是否能够满足这些约束。
如果您认为需要延迟数据信号，则表明您有暂停时间问题，但您的UCF线路仅指定设置时间。
假设您的信号在时钟边沿之前5 ns有效，但保持时间为1 ns，这意味着它在时钟边沿之前1 ns已经无效。
这个语法是：
NET“chana_rd”OFFSET = IN 5 ns有效4 ns之前“chana_rxclk”;
“有效4 ns”定义了总有效窗口宽度。
因此，有效窗口在时钟前5 ns开始，并在4 ns后或时钟前1 ns结束。
有了这个约束，工具将尝试满足建立和保持时序，并可能在输入数据路由中添加一些延迟来实现这一点。
在某些情况下，工具无法添加您请求的延迟。
如果输入寄存器放在IOB中，或者时钟和数据之间的关系使得它们无法通过路由延迟来修复时序，则可能发生这种情况。
此时，您需要更改设计，使用DCM或PLL等时钟组件来更改时钟相位，或者在输入数据路径中添加IDELAY组件。
-  Gabor



以下为原文

The only thing you can do with UCF constraints is to define the valid window (setup and hold timing) and see if the tools are able to meet these constraints.  If you think you need to delay the data signal, it appears that you have a hold time issue, but your UCF line only specifies the setup time.  Let's assume that your signal becomes valid 5 ns before the clock edge, but has a negative hold time of 1 ns, meaning it is already invalid 1 ns before the clock edge.  The syntax for this is:
 
NET "chana_rd" OFFSET = IN 5 ns valid 4 ns BEFORE "chana_rxclk"  ;
 
The "valid 4 ns" defines the total valid window width. So the valid window starts 5 ns before the clock and ends 4 ns later, or 1 ns before the clock.  With this constraint, the tools will try to meet setup and hold timing, and might add some delay in the input data routing to achieve this.
 
There are some cases where the tools cannot add the delay you requested.  This could happen if the input register is placed in the IOB, or if the relationship between clock and data is such that they can't fix the timing with routing delays.  At that point you would need to change the design, either using a clock component like DCM or PLL to change the clock phase, or by adding an IDELAY component in the input data path.
-- Gabor

因此，我应该将有效时间设置为长于OFFSET BEFORE时间以满足保持时间要求。
我应该使用7 ns而不是4ns吗？
NET“chana_rd”OFFSET = IN 5 ns有效7ns BEFORE“chana_rxclk”;
谢谢



以下为原文

So should I set the valid time longer than the OFFSET BEFORE time to meet the hold time requirement. Should I use maybe 7 ns instead of 4ns instead? 
 
NET "chana_rd" OFFSET = IN 5 ns valid 7 ns BEFORE "chana_rxclk"  ;
 
Thanks

您应该使约束与FPGA在硬件中看到的实际信号相匹配。
如果您的正保持时间为2 ns，那么约束在您编写时是正确的。
基本上，约束是告诉工具你实际必须满足的时间。
-  Gabor



以下为原文

You should make the constraint match the actual signal that the FPGA will see in the hardware.  If you have a positive hold time of 2 ns, then the constraint is correct as you wrote it.  Basically the constraint is there to tell the tools what timing you actually have to meet.
-- Gabor