LUT和Kintex 7 FPGA芯片中的FF所需的资源

嗨，
只是一些评论：
1）为了您的目的，考虑使用或不使用LUT的事实是不够的：可能发生LUT仅用于路由信号而另一个LUT用于执行6输入逻辑功能。
2）设计的实现可以根据与功能本身无关的其他规范而变化，例如，时序约束，引脚位置，速度区指令，FPGA占用等。
3）为了使用简化的A * N + B方程，您需要知道LUT和FF中使用的晶体管数量，我认为您不会知道（这取决于Xilinx技术）。
即使您知道，当设计实现不受给定的固定架构（FF和LUT）影响时，所需的晶体管数量也会有所不同。
例如，移位寄存器的实现可能会有很大差异，具体取决于在定位芯片中的实际硬件组件时HDL代码中描述的方式（在SRL16的情况下可以使用少量LUT实现或使用
更多的FF）。
4）如何在等式中包含其他元素，如DSP48或BRAM？
也就是说，我认为了解芯片中每种资源的占用情况更为重要。
那应该够了。
祝你好运，
IKERLAN FPGAfpga@ikerlan.es
在原帖中查看解决方案



以下为原文

Hi,
 
Just some comments:
 
1)      For you purpose, the fact of considering a LUT used or not used is not enough: it may happen that a LUT is used just to route a signal through and another LUT is intensively used to perform a 6-input logic function.
2)      The implementation of a design may vary depending on other specifications which are not related to the functionality itself, e.g., timing constraints, pin locations, speed-area directives, FPGA occupation, etc.
3)      In order to use your simplified A*N+B equation,  you need to know the amount of transistors used in the LUTs and FFs, which I do not think you will ever know (this is dependent on Xilinx technology). Even if you knew, the real amount of transistors needed would vary when the design implementation is not subject to a given fixed architecture (FF and LUTs). For instance, the implementation of a shift-register can vary a lot depending on the way it is described in the HDL code when targeting the real hardware components in the chip (it may be implemented using a few LUTs in the case of SRL16 or using a greater number of FFs).
4)      How would you include other elements, such as DSP48s or BRAMs, in your equation?
 
That said, I think it is much more relevant to give an idea of the occupation of each of the resources in the chip. That should be enough.
 
Good luck,
IKERLAN FPGA
fpga@ikerlan.esView solution in original post

没有办法做你想做的事。
不可能获取LUT和FF的数量并计算相应数量的ASIC门（无论是什么），标准单元，晶体管或芯片面积。
由恒定因子组成的任何转换都更加虚假。
如果要进行有意义的比较，请比较同一FPGA系列上的不同实现。
任何其他东西都会给你毫无意义的数字。
注意：在给定的FPGA上，设计X比设计Y更小/更快，因为设计Y的因数为u，这样就无法表明这些设计在ASIC上如何相互比较。
请在询问之前先查询您的问题。如果有人回答您的问题，请在“接受为解决方案”标记该帖子。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的星）。



以下为原文

There is no way of doing what you want to do. It is not possible to take the number of LUTs and FFs and calculate the corresponding number of ASIC gates (whatever that is), standard cells, transistors, or chip area. Any conversion consisting of a constant factor is even more bogus.
 
If you want to do a meaningful comparison, compare different implementations on the same FPGA family. Anything else will give you meaningless numbers.
 
Note: A design X being smaller/faster then a design Y by a factor of u on a given FPGA will give you no indication of how these designs would compare to each other on an ASIC.

Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).

谢谢你的快速回答。
我知道ASIC门和FPGA LUT-FF之间的转换是不相关的。
我的问题是在Kintex 7 FPGA中比较LUT与FF的资源。
我想要做的是评估算术设备的复杂程度。
例如，浮点加法器需要500个LUT和668个FF，
根据产品指南，浮点乘法器需要574个LUT和683个FF。
在这种情况下哪一个比另一个更复杂（计算成本高）？
如果我知道LUT需要N次，例如晶体管比FF那么多，
我可以将复杂性度量计算为A * N + B，其中A和B是LUT的数量
和FF分别。
最好的祝福，
杰瑞安。



以下为原文

Thank you for the quick answer.
 
I understand that conversion between ASIC gates and FPGA LUT-FF is not relevant.
My question is about comparing the resources for an LUT against FF, in Kintex 7 FPGA.
 
What I am trying to do is to evaluate the measure of complexity for arithmetic devices.
For example, a floating-point adder require 500 LUTs and 668 FFs,
and a floating-point multiplier require 574 LUTs and 683 FFs, according to the product guide.
In this case which one is more complex (computationaly expensive)  than the other ?
If I know that a LUT needs N time more, for example, transistors than an FF do,
I can calculate a complexity measure as A * N + B, where A and B is the numbers of LUTs
and FFs, respectively.
 
Best Regards,
Jerry Ahn.
 

嗨，
只是一些评论：
1）为了您的目的，考虑使用或不使用LUT的事实是不够的：可能发生LUT仅用于路由信号而另一个LUT用于执行6输入逻辑功能。
2）设计的实现可以根据与功能本身无关的其他规范而变化，例如，时序约束，引脚位置，速度区指令，FPGA占用等。
3）为了使用简化的A * N + B方程，您需要知道LUT和FF中使用的晶体管数量，我认为您不会知道（这取决于Xilinx技术）。
即使您知道，当设计实现不受给定的固定架构（FF和LUT）影响时，所需的晶体管数量也会有所不同。
例如，移位寄存器的实现可能会有很大差异，具体取决于在定位芯片中的实际硬件组件时HDL代码中描述的方式（在SRL16的情况下可以使用少量LUT实现或使用
更多的FF）。
4）如何在等式中包含其他元素，如DSP48或BRAM？
也就是说，我认为了解芯片中每种资源的占用情况更为重要。
那应该够了。
祝你好运，
IKERLAN FPGAfpga@ikerlan.es



以下为原文

Hi,
 
Just some comments:
 
1)      For you purpose, the fact of considering a LUT used or not used is not enough: it may happen that a LUT is used just to route a signal through and another LUT is intensively used to perform a 6-input logic function.
2)      The implementation of a design may vary depending on other specifications which are not related to the functionality itself, e.g., timing constraints, pin locations, speed-area directives, FPGA occupation, etc.
3)      In order to use your simplified A*N+B equation,  you need to know the amount of transistors used in the LUTs and FFs, which I do not think you will ever know (this is dependent on Xilinx technology). Even if you knew, the real amount of transistors needed would vary when the design implementation is not subject to a given fixed architecture (FF and LUTs). For instance, the implementation of a shift-register can vary a lot depending on the way it is described in the HDL code when targeting the real hardware components in the chip (it may be implemented using a few LUTs in the case of SRL16 or using a greater number of FFs).
4)      How would you include other elements, such as DSP48s or BRAMs, in your equation?
 
That said, I think it is much more relevant to give an idea of the occupation of each of the resources in the chip. That should be enough.
 
Good luck,
IKERLAN FPGA
fpga@ikerlan.es