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[问答]

DCM怎么避免输出的延迟

嗨,
我在使用DCM时遇到了问题。我的要求实际上是将clk信号的频率从50MHz降低到20MHz。在10个时钟脉冲之后,dcm的输出会显示出来。
我使用的是ISE版本12.1。
FPGA系列:Spartan 3E
设备:XC3S250E
包装:CP132
速度:-4
使用的DCM属性:
CLK_FEEDBACK = NONE CLKDV_DIVIDE = 2.5 CLKFX_DIVIDE = 5 = CLKFX_MULtiPLY 2 CLKIN_DIVIDE_BY_2 = FALSE CLKIN_PERIOD = 20.000 CLKOUT_PHASE_SHIFT = NONE DESKEW_ADJUST = SOURCE_SYNCHRONOUS DFS_FREQUENCY_MODE = LOW DLL_FREQUENCY_MODE = LOW DUTY_CYCLE_CORRECTION = TRUE FACTORY_JF = 16'hC080 PHASE_SHIFT = 0 STARTUP_WAIT = FALSE
是否有任何设置更改我需要实现以避免输出的延迟。如果不是我想知道,如果任何其他方式我可以实现这个信号。

以上来自于谷歌翻译


以下为原文

Hi,
     I have an issue in using a DCM.My requirement is actually to cut down the frequency of clk signal from 50MHz to 20 MHz.The output of a dcm is getting displayed after 10 clock pulses.

I am using ISE version 12.1.
FPGA family:Spartan 3E
Device:XC3S250E
PAckage:CP132
speed:-4
The DCM attributes used :
CLK_FEEDBACK = NONE
CLKDV_DIVIDE = 2.5
CLKFX_DIVIDE = 5
CLKFX_MULTIPLY = 2
CLKIN_DIVIDE_BY_2 = FALSE
CLKIN_PERIOD = 20.000
CLKOUT_PHASE_SHIFT = NONE
DESKEW_ADJUST = SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE = LOW
DLL_FREQUENCY_MODE = LOW
DUTY_CYCLE_CORRECTION = TRUE
FACTORY_JF = 16'hC080
PHASE_SHIFT = 0
STARTUP_WAIT = FALSE

Is there any setting changes i needs to implement to avoid the latency at the output.If not i would like to kno if any other way i can acheive this signal.





回帖(8)

杨玲

2019-1-30 09:09:44
您无法真正避免延迟,因为DCM需要时间来锁定输入信号。
如果您只想将输入时钟除以2.5,那么您可以使用结构触发器代替
一个DCM。
这种方法的缺点是产生的20 MHz信号不会
相位与输入时钟对齐。
顺便说一句,你的应用程序需要在重置后如此快地运行时钟?
-  Gabor
-  Gabor

以上来自于谷歌翻译


以下为原文

You can't really avoid the delay because the DCM needs time to lock to the input signal.
 
If all you want is to divide the input clock by 2.5, then you could use fabric flip-flops instead
of a DCM.  The down side to this method is that the resulting 20 MHz signal will not be
phase aligned with the input clock.
 
By the way, what is your application that needs the clock running so soon after reset?
 
-- Gabor
-- Gabor
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陈蓓萤

2019-1-30 09:22:28
为什么不通过合并现有的重置和DCM锁定状态输出端口来生成另一个重置信号?
这会解决你的整体问题吗?

以上来自于谷歌翻译


以下为原文

Why don't you generate another reset signal by comining your existing reset and the DCM locked status output port?  Will that solve your overall problem?
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徐非姗

2019-1-30 09:41:38
嗨Gabor,
谢谢你的回复!!!
实际上,该信号用于为ADC提供时钟.ADC的输入来自传感器设备,该传感器设备仅存在很短的时间。因此我希望ADC能够立即响应以提高系统效率并使用此功能。
DCM用于更好的抖动管理,我认为使用触发器无法在很大程度上避免这种情况。如果我对我所做的观察错误,请告诉我。

以上来自于谷歌翻译


以下为原文

Hi Gabor,
 
Thanks for ur reply!!!
 
Actually the signal is used to clock an ADC.and the input to the ADC is from a sensor device which will be present for only a short duration of time.So i wanted ADC to respond immediately to make the system more efficient and i used this DCM for better jitter management which i guess could not  be avoided to a large extend by using flip-flop.Please advice me if i am wrong with the observations i made.
举报

徐非姗

2019-1-30 09:50:42
Re:DCM问题
11-10-201104:31 PM
为什么不通过合并现有的重置和DCM锁定状态输出端口来生成另一个重置信号?
这会解决你的整体问题吗?
嗨, 
如果你能详细描述那将是很棒的。甚至我用复位信号尝试了所有的可能性。延迟发生了。
:smileysad:

以上来自于谷歌翻译


以下为原文

Re: DCM issue

 11-10-2011 04:31 PM
Why don't you generate another reset signal by comining your existing reset and the DCM locked status output port?  Will that solve your overall problem?
 
 
Hi,
  It will be greatful if u could elaborate the description.And even I tried all the possibilities with the reset signal.Again the delay is occuring. :smileysad:
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