如何使用DCM生成低频脉冲？

嗨Anil，
使用计数器从任何高时钟频率产生10 Hz范围内的频率应该有效。
DCM与它无关，因此主题标题令人生气。
但究竟是什么产生的呢？
50％占空比脉冲，或单个1 / 100MHz脉冲，重复频率为10 Hz（例如，用于时钟使能目的？
第一个应该在任何示波器上清晰可见，而第二个有点难以显示。
（需要高带宽和高采样率示波器，例如200 MHz，1GSPS）
向我们展示一些代码，以便我们可以看到您正在做什么。
有一个很好的综合 
Eilert



以下为原文

Hi Anil,
generating frequencies in thge 10 Hz Range from any high clock frequency with a counter should work.
The DCM has nothing to do with it, so the thread title is irritating.
 
But what exactly do you generate? A 50% duty cycle pulse, or a single 1/100MHz impulse with a repetitipon rate of 10 Hz (e.g. for Clock enable purposes?
The first one should be clearly visible on any oscilloscope, while the second one is somewhat harder to display. (Needs a high bandwith and high sample rate oscilloscope e.g. 200 MHz, 1GSPS)
Show us some code so we can see what exactly you are doing.
 
Have a nice synthesis
  Eilert

我希望你实际上计算0到99.这将给你你的除以100达到1 MHz。
约翰普罗塞纳



以下为原文

I hope you're actually counting 0 to 99.  That will give you your divide by 100 to get to 1 MHz.
 
 
 
John Providenza

嗨，eilert，
我的问题已解决。
我使用的数量较少。
我还有一个问题。
我能够在DCM中正确生成10 MHz到100Mhz但是当我生成10 MHz到200Mhz时，
它产生20个时钟周期但延迟到10Mhz clk结束然后产生20个周期，同样继续.... 
- 组件声明
COMPONENT dcm_prt_pw PORT（CLKIN_IN：IN std_logic; CLKFX_OUT：OUT std_logic; CLKIN_IBUFG_OUT：OUT std_logic; LOCKED_OUT：OUT std_logic）;
结束组成部分;
- 组件实例化 
Inst_dcm_prt_pw：dcm_prt_pw端口映射（CLKIN_IN => clk_fpga，CLKFX_OUT => clk_int，CLKIN_IBUFG_OUT =>打开，LOCKED_OUT => locked_int）;



以下为原文

Hi eilert,
 
My problem is fixed. I was using less count. I have one more problem.
I could able to generate 10 MHz to 100Mhz in DCM properly But when i go to generate  10 MHz to 200Mhz,
 
It generates 20 clock cycles but a delay till the 10Mhz clk ends and then generates 20 cycles, same continues....
 
   
-- component declarations
 
COMPONENT dcm_prt_pw
    PORT(
        CLKIN_IN : IN std_logic;         
        CLKFX_OUT : OUT std_logic;
        CLKIN_IBUFG_OUT : OUT std_logic;
        LOCKED_OUT : OUT std_logic
        );
    END COMPONENT;
 
 
-- component instantiation
 
    Inst_dcm_prt_pw: dcm_prt_pw PORT MAP(
        CLKIN_IN => clk_fpga,
        CLKFX_OUT => clk_int,
        CLKIN_IBUFG_OUT => open,
        LOCKED_OUT => locked_int
    );

您好
两件事情。
根据设备的不同，您的DCM能否工作在10 MHz输入时钟？
您使用clk_fx输出（同样取决于设备）并不完全是“对称的”。



以下为原文

HI
 
two things.
 
Depending upon the device, does your DCM work down to a 10 MHz input clock ?
 
Your using the clk_fx output, which again depending upon the device, is not exactly 'symetrical'.