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[问答]

添加Chipscope会导致错误

我有一个与Synopsys Protocompiler合成的设计。
目标是XilinxXC7VX980TFFG1926-2,使用不到40%的luts。
Vivado没有问题,没有Chipscope。
当我添加带有38个探针和4k样本深度的ILA时,Vivado失败并出现以下错误:
启动功率优化TaskINFO:[Pwropt 34-132]跳过具有周期的时钟的时钟门控错误:[Pwropt 34-195]功率优化遇到错误:'错误:[通用17-70]应用程序异常:LUT超过6
输入。
跳过功率优化。
是什么导致这个错误?

以上来自于谷歌翻译


以下为原文

I have a design that is synthesized with Synopsys Protocompiler.
The target is a Xilinx XC7VX980TFFG1926-2 and uses less then 40% of the luts.
Vivado has no problem without Chipscope.

When I add an ILA with 38 probes and 4k sample depth Vivado fails  with the following error :
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.12 ns.
ERROR: [Pwropt 34-195] Power optimization encountered an error: 'ERROR: [Common 17-70] Application Exception: LUT with more than 6 inputs
'. Skipped power optimization.

What causes this error?

回帖(2)

姚庭芳

2018-10-30 11:23:29
你好@ meessen
你用ILA探测时钟网了吗?
2.减少ILA探测器的数量,并尝试在设计上运行opt_design
3.共享完整的日志文件,这可能有助于调试问题。
谢谢,
维奈
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以上来自于谷歌翻译


以下为原文

Hi @meessen
 
1. Did you probe the clock net using ILA?
2. Reduce number of ILA probes and try running opt_design on the design
3. Share the complete log file which may help in debugging the issue.
 
Thanks,
Vinay
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吕钢格

2018-10-30 11:30:55
嗨@ meessen,
请尝试以下步骤,让我们知道结果:
删除调试核心,然后在Synplify中生成.edf文件
将.edf文件添加到Vivado
使用“设置调试”插入ILA
谢谢,Arpan
谢谢,Arpan -----------------------------------------------
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------------------------

以上来自于谷歌翻译


以下为原文

Hi @meessen,
 
Please try the following steps and let us know the outcomes:

  • Remove debug core and then generate .edf file in Synplify
  • Add .edf file to Vivado
  • Use "set up debug" to insert ILA
Thanks,
Arpan
Thanks,
Arpan
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