完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
亲爱的大家,
我在使用ChipScope进行调试时遇到了一个非常奇怪的问题。 我使用ML605板通过FMC HPC接口控制和与CMOS传感器通信。 我的设计被正确模拟,但我没有成功实现设计(标志信号没有断言)。 然后我添加了ChipScope进行调试,没有任何代码更改,我的设计已经成功实现。 所有信号都由ChipScope正确显示。 此外,在另一种设计中,除了添加ChipScope调试器之外,我无法从双端口RAM读出正确的数据。 这让我很困惑。 ChipScope会影响信号的时序还是优化信号的路径和位置? 我很感激任何帮助。 干杯 以上来自于谷歌翻译 以下为原文 Dear all, I met a very strange issue when I was debugging with ChipScope. I used ML605 board to control and communicate with a CMOS sensor via FMC HPC interface. My design was correctly simulated, but I was not successful to implement the design (Flag signals did not assert). Then I added ChipScope to debug, without any changing of code, my design has been successfully implemented. And all the signals are correctly displayed by ChipScope. Furthermore, in an other design, I can not read out the correct data from a dual port ram only except adding a ChipScope debugger. It really confuse me. Does ChipScope affect the timing of signals or it optimize signals' route and place? I am grateful for any help. Cheers |
|
相关推荐
10个回答
|
|
检查综合和地图报告,确保您的逻辑没有得到优化。
听起来你的设计的一部分没有正确连接到输出并且正在优化。 以上来自于谷歌翻译 以下为原文 Check your synthesis and map reports to make sure your logic is not getting optimized out. It sounds like part of your design is not connected correctly to an output and is getting optimized out. |
|
|
|
不太可能,但地图可能会错误地优化部分设计。
您可以尝试在地图选项中启用“忽略保持层次结构”。 以上来自于谷歌翻译 以下为原文 Not likely but map could be falsely optimizing part of the design out. You could try enabling the "ignore keep hierarchy" in the map options. |
|
|
|
你的设计在两种情
您正在应用时序约束,并检查它们是否正确? 以上来自于谷歌翻译 以下为原文 Does your design pass timing in both cases? You are applying timing contraints, and checking them correct? |
|
|
|
嗨ddemmin,
感谢您的回复。 我尝试启用“忽略保持层次结构”,但问题仍然存在,并且两种情况都没有计时错误。 这真的很奇怪,如果不添加ChipScope,我就永远不会成功。 非常感谢 以上来自于谷歌翻译 以下为原文 Hi ddemmin, Thanks for your reply. I tried enabling the "ignore keep hierarchy", but the problem still existed, and both case have no timing error. It is really strange, and I have never succeed without adding ChipScope. Many thanks |
|
|
|
嗨Markcurry,
我确信在这两种情况下都没有时序约束错误。 我添加了ChipScope而没有改变任何属性。 有什么建议么? 我使用的是ISE 12.4版本 干杯 以上来自于谷歌翻译 以下为原文 Hi Markcurry, I am sure there are not timing constraint errors in both case. And I added the ChipScope without changing any properties. Any suggestions? I am using ISE 12.4 version Cheers |
|
|
|
我仍怀疑时机。
您定位的频率是多少? 您的ucf文件中有哪些TIG? 你确定你所有的约束都是正确的吗? 您是否正确约束了所有IO的设置/保持时间? 我遇到过像你这样的问题 - 添加切屑镜改变行为 - 这通常是我的约束问题。 我错误地应用了约束,或者错误地创建了错误的路径。 无论如何我的经历。 关于错过时间的其他事项: http://www.xilinx.com/support/answers/42444.htm 以上来自于谷歌翻译 以下为原文 I'd still suspect timing. What frequencies are you targeting? What TIGs are in your ucf file? Are you sure that all your constraints are correct? Have you properly constrained all IOs for setup/hold times? Where I've had problems such as yours - adding chipscope changing the behaviour - it's usually a problem with my constraints. I've mistakenly applied constraints, or incorrectly created false paths. My experience anyway. Other things to consider with respect to missed timing: http://www.xilinx.com/support/answers/42444.htm |
|
|
|
正如马克所说。
列出您正在使用的点击次数以及与之相关的约束条件。 您的所有时钟都在全局或区域时钟缓冲区吗? 以上来自于谷歌翻译 以下为原文 As mark said. List the clicks you are using, and what constraints you have associated with them. Are all of your clocks on global or regional clock buffers? |
|
|
|
嗨markcurry,
非常感谢您的回复,这真的很有帮助。 我是FPGA的新手,我无法理解时序约束。 对于我的应用程序(ucf文件),我只是将输入/输出端口映射到正确的引脚,并仅定义全局时钟信号的时序约束。 这是问题的主要问题吗? 我附上了我的ucf文件,如果你能快速浏览一下,我将非常感激。 干杯 image.ucf 4 KB 以上来自于谷歌翻译 以下为原文 Hi markcurry, Many thanks for your reply, it is really helpful. I am very new to FPGA, and I can not understand timing constraints well. For my application (ucf file), I just map the in/out port to the correct pin and only define the timing constraint of the Global clock signals. is this the main problem of the issue? I attached my ucf file, and if you can have a quick look , I will be very grateful. Cheers image.ucf 4 KB |
|
|
|
嗨ddemmin,
我附上了我的ucf文件,并检查了设计,所有时钟都在时钟缓冲区上。 干杯 以上来自于谷歌翻译 以下为原文 Hi ddemmin, I attached my ucf file, and I checked the design, all clocks are on clock buffers. Cheers |
|
|
|
你在UCF中对抗时钟,这很好。
但不是IO - 这很糟糕。 我们暂时跳过IO,(根本不是一个安全的假设,但我们必须从某个地方开始。)。 当你运行trce时,你对输出有什么看法? 它应该说: 时间总结:---------------计时错误:0得分:0(设置/最大:0,保持:0) 你看到了什么结果? 任何非零结果? 我怀疑你不会在这里看到全部的零。 我错了...... 以上来自于谷歌翻译 以下为原文 You're contraining clocks in the UCF, that's good. But not IO - that's bad. Let's skip IO for now, (not a safe assumption at all but we've got to start somewhere.). When you run trce, what do you get at the output? It should say something like: Timing summary: --------------- Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) What results do you see? Any non-zero results? I have a suspicion that you're not going to see all zeros here. I could be wrong... |
|
|
|
只有小组成员才能发言,加入小组>>
2420 浏览 7 评论
2823 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2294 浏览 9 评论
3374 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2461 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
1157浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
584浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
450浏览 1评论
2005浏览 0评论
729浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-23 02:36 , Processed in 1.341782 second(s), Total 66, Slave 60 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号