ILA存在时实施失败

300 MHz是默认值：它不会查看您的设计以确定时钟频率。
丹尼尔
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以下为原文

300 MHz is the default: it does not look into your design to determine what the clock frequency is.
 
Daniel
 
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ILA为您的设计添加了更多逻辑，这可能导致失败。
我经常做的是获取感兴趣的信号，通过几个寄存器计时，然后将它们运行到VIO模块中。
然后我让ILA探测VIO模块输入端的信号。
这将允许实现将感兴趣的逻辑从关键时序路径移动到不会影响您的设计的区域。
是的，您需要分配调试时钟并设置实际频率。
如果右键单击设计中的dbg_hub并获取单元属性：
然后你会看到你可以在哪里设置时钟频率和其他选项。
丹尼尔



以下为原文

ILA adds more logic to your design, and that can be causing the fail.  What I will often do is take the signals of interest, clock them through a few registers and then run them into a VIO module.  Then I get ILA to probe the signals at the input to the VIO module.  That will allow the implementation to move the logic of interest out of the critical timing paths into an area where it will not effect your design.
 
And yes, you need to assign a debug clock and set the actual frequency.  If you right click on the dbg_hub in your design and get cell properties:
 

 
Then you see where you can set the clock frequence and other options.
 

 
Daniel
 

嗨，如果您试图通过将它们连接到ILA来探测设计中的任何时钟，这可能会影响保持时序，因为它会在时钟路径中插入luts。
请检查这是否是问题。谢谢，Deepika。
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以下为原文

Hi,

In case if you are trying to probe any clocks in your design by connecting them to ILA this may affect hold timing as it inserts luts in the clock path. Please check if this is the problem.

Thanks,
Deepika.Thanks,
Deepika.
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插入ILA时的时序故障可以是两种类型1. ILA本身的故障路径2. dbg_hub中的故障路径
在第一种情况下，确保探头宽度小于200
在第二节，上面提到的约束将会出现。
让我们举两个例子1.只有一个ILA @ 300Mhz
在这种情况下，dbg_hub时钟和ILA时钟将是相同的
所以你必须使用下面的约束来消除dbg_hub中的任何计时故障
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]
此值“300000000”应与freq（以hz为单位）相同，与连接到dbg_hub块的时钟相同
现在是第二个例子，有两个ILA的1 @ 300＆amp;
2 @ 250
在这种情况下，dbg_hub时钟也会获得上述时钟之一（300或250）
现在对dbg_hub使用相同的约束，并根据连接到dbg_hub模块的时钟正确设置hq中的freq值
上面提到的两个约束是通过使用MMCM来降低dbg_hub模块的频率
内部set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]
如果此属性设置为false，则不会对任何MMCM进行实例化...
希望这可以帮助。
问候
Sikta



以下为原文

The timing failures when ILA is inserted can be of two types
1. The failure paths in ILA itself
2. The failure paths in dbg_hub
In 1st case make sure your probe width is less 200
In 2nd the constraint mentioned above will come into picture.
lets take two examples 
1. Only one ILA @ 300Mhz
In this case the dbg_hub clock and ILA clock will be same
so you have to use below constraints to eliminate any timing failures in dbg_hub
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]
This value "300000000" should be same as the freq (in hz) as that of clock connected to dbg_hub block
 
and now 2nd example
with two ILA's 1 @ 300 & 2 @ 250
In this case also dbg_hub clock gets one of above clocks (either 300 or 250)
now use same constraints above for dbg_hub and properly set the freq value in hz based on the clock connected to dbg_hub module
above mentioned two constraints are to reduce frequency for dbg_hub module by using an MMCM
internally set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]
if this property is set to false there wont be any MMCM instantiated...
 
Hope this helps.
 
Regards
Sikta