使用Planahead导入项目怎么将微胶片转换为黑盒子

你好，
当导入和现有的ISE项目进入planahead时，我收到一些严重的警告。
我试图为我的项目创建一个平面图。
令我非常困惑的一件事是，如果我去ISE>用户约束>布局规划区域逻辑，它打开项目就好了，导入微型灯很好，但是用这种方法我无法编译或查看布局规划器本身的时间来制作
根据需要调整我的pblocks，除非有一个我缺少的方法。
如果我自己打开planahead，并使用新项目>导入的项目创建一个新项目并选择我的ise项目，并运行综合我收到以下两个严重警告，我通过其他方法打开时没有收到：
[EDIF 96]无法解析在文件'main.ngc'中定义的非原始黑盒子单元'microblaze_sys'，实例化为'Inst_microblaze_sys'。
[Designutils 977]找不到ref fast_clock。
此参考不会读取UCF文件d： Cosmiac Local Floorplan CubeSat CubeSat.srcs sources_1 ip fast_clock fast_clock example_design fast_clock_exdes.ucf。
我尝试使用floorplanner约束的这个项目的主要部分是microblaze_sys。
我仍然能够右键单击并选择绘制pblock，但是我所拥有的问题是估计的物理资源列表没有填充因此我不知道我需要什么切片编号brams数字等以便在芯片上绘制区域
。
我已经读过这是一个已知的bug，可以安全地被忽略，但因为那个列表没有填充忽略它会引起其他问题，我不知道如何解决

以上来自于谷歌翻译

以下为原文

Hello,

I am getting a few critical warnings when importing and existing ISE project into planahead. Im attempting to create a floorplan for my project.

One thing that is greatly confusing me is if i go to ISE > User Constraints > Floorplan Area Logic it opens the project just fine, importing the microblaze just fine, however with this method i can not compile or look at timing in floorplanner itself to make adjustments as needed with my pblocks, unless there is a method that i am missing.

If i open planahead on its own, and create a new project using the new project > imported project and select my ise project, and run synthesis i recieve the two following critical warnings that i do not recieve when opening via the other method:

[EDIF 96] Could not resolve non-primitive black box cell 'microblaze_sys' defined in file 'main.ngc' instantiated as 'Inst_microblaze_sys'.

[Designutils 977] Could not find ref fast_clock. The UCF file d:CosmiacLocalFloorplanCubeSatCubeSat.srcssources_1ipfast_clockfast_clockexample_designfast_clock_exdes.ucf will not be read for this ref.

The main part of this project i am trying to constrain using floorplanner is the microblaze_sys. I am still able to right click and select draw pblock, however the issue im having is that the estimated physical resources list is no populating so i do not know what slice number brams number etc that i need in order to draw the area on the chip.

I have read that this is a known bug and can safely be ignored, but because that list is not populating ignoring it gives rise to other problems that I do not know how to solve

王飞云

2018-10-16 13:31:08

cosmiac，
如果您将此帖发布在论坛的“设计工具”部分，我想您会收到更好的回复。
该区域专用于Xilinx开发板和套件。
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-----------------------不要忘记回答，kudo，并接受为解决方案.-------------
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以上来自于谷歌翻译

以下为原文

cosmiac,

I think you would receive a better response to this post if you posted it in the Design Tools section of the forum. This area is dedicated to Xilinx Boards and Kits.
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Don’t forget to reply, kudo, and accept as solution.
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