赛灵思
直播中

俞敏东

7年用户 239经验值
私信 关注
[问答]

placemenet和从Virtex5到zynq设备的路由出现错误

你好,
我正在尝试在zynq设备上实现一个设计。
我已经在Virtex5设备上实现了它,它的工作非常好。
但是当我更改设备时,我在放置和路由阶段得到了以下错误。我更改了UCF文件,但我不明白这个错误是什么意思!
为什么它适用于Virtex5而不适用于zynq设备?
谢谢,
纳吉姆
错误:Pack:1107  -  Pack无法将下面列出的符号组合到单个IOB组件中,因为所选的站点类型不兼容。
进一步说明:组件类型由逻辑类型及其包含的逻辑的属性和配置决定。
在这种情况下,选择类型为IOB的IO组件,因为IO包含与输入,输出或双向使用一致的符号和/或属性,并且不包含需要更具体的IO组件类型的其他符号或属性。
请仔细检查逻辑元素的类型及其所有相关属性和配置选项是否与约束的物理站点类型兼容。
摘要:涉及的符号:BUF符号“rx_i_IBUF”(输出信号= rx_i_IBUF)PAD符号“rx_i”(填充信号= rx_i)涉及的组件类型:涉及的IOB站点位置:涉及的D11站点类型:IOPAD

以上来自于谷歌翻译


以下为原文

Hello,

I am trying to implement a design on zynq device. I had implemented it on Virtex5 device and it works verry good. But when i change the device i got the error below in the placement and route phase. I changed the UCF file but i don't understand what is the meaning of this error ! and why it works on Virtex5 and not on zynq device ?

Thank you,
Najem

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOB was chosen because the IO contains symbols and/or properties consistent
   with input, output, or bi-directional usage and contains no other symbols or
   properties that require a more specific IO component type. Please double
   check that the types of logic elements and all of their relevant properties
   and configuration options are compatible with the physical site type of the
   constraint.

   Summary:
   Symbols involved:
       BUF symbol "rx_i_IBUF" (Output Signal = rx_i_IBUF)
       PAD symbol "rx_i" (Pad Signal = rx_i)
   Component type involved: IOB
   Site Location involved: D11
   Site Type involved: IOPAD            



回帖(5)

潘晶燕

2018-10-15 12:01:19
http://www.xilinx.com/support/answers/25058.htm
虽然不完全是你的问题(它是关于输出,你的问题是一个输入)它确实描述了你需要寻找的东西(at)。
Austin Lesea主要工程师Xilinx San Jose

以上来自于谷歌翻译


以下为原文

http://www.xilinx.com/support/answers/25058.htm
 
Although not exactly your problem (it is about an output, your problem is an input) it does describe what you need to look for (at).
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose
举报

石俊梅

2018-10-15 12:12:10
嗨,
一个小的检查。检查UART ppins是否受限于EMIO引脚。
谢谢,
迪皮卡。
谢谢,迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星)

以上来自于谷歌翻译


以下为原文

Hi,
 
one small check..Check if the UART ppins are constrained to EMIO pins.
 
Thanks,
Deepika. 
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
举报

励黎

2018-10-15 12:20:38
None
以上来自于谷歌翻译


以下为原文

Hi, I have the similar problem.
The UART tx/rx on Zynq ZedBoard is PS_MIO48-49
I think that means they conect only to PS side, not PL side.
 
I use XPS Zynq PS MIO Configurations to change their parameters:
 
UART1 MIO 48-49 Modem Signals EMIO and I succeeded to have all the control signals out of the PS.
 
BUUUUUUUUUUUUTTTTT, where is TX and RX? They are not in the list !!!
So HEEEEEEEEEEEELP!
 
Lily
举报

潘晶燕

2018-10-15 12:31:57
百合,
试着询问:
zedboard.org
这是zedboard的“官方”支持页面。
截至昨天,有关Zynq的问题在那里发布了27个新问题(而不是8个问题)。
并不是说有人可能不会帮助你,但是去参加专门讨论zedboards的论坛并且有一个非常活泼,专注的社区是很有意义的。
Austin Lesea主要工程师Xilinx San Jose

以上来自于谷歌翻译


以下为原文

Lily,
 
Try asking on:
 
zedboard.org
 
Which is the 'official' support page for the zedboard.

As of yesterday, there were 27 new questions posted there (as opposed to 8 here) concerning Zynq.
 
Not that someone might not help you out here, but it makes sensse to go to the forum that is dedicated to the zedboards, and has a very lively, and dedicated, community.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose
举报

更多回帖

发帖
×
20
完善资料,
赚取积分