Nvidia is hiring-Senior DFT Engineer

2016-7-15 13:58:30 2036

0 本帖最后由 CarraZ 于 2016-7-15 15:43 编辑 Hi, Here is a position that we are hiring in Shanghai. The following is the Job Description of this position-- DFT Engineer. If someone is interested, plz feel free contact me and sent cv to my e-mail address. Thank you. Here is my E-mail: carraz@nvidia.com Location: No.26, QiuYue road, New Pudong district, Shanghai(Near Line 2,GuangLan road) Position Title: Senior DFT Engineer Responsibilities: · Planning at IP or fullchip level. · Implementation and verification for MBIST/Scan/LBIST/ATPG. · Design/verification for Clock/JTAG/Analog/DFT IP etc. · Pattern generation, release and ATE bringup. · Responsiblefor DFT design/methodology/flow improvements. Requirements: · BSEE required, MSEE preferred. · 3~10years of experience in DFT/design field. · Strong logic Design and verification background with experience in STA. · Must possess a strong knowledge of DFT including Scan, ATPG, Test Compression, JTAG and BIST. · Capability to do DFT methodology work. · Self-motivated and good team player. Carra 021-61049073 0
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