【创龙TMS320C665x开发板试用】基础（九）： DDR3

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` 本帖最后由 jinyi7016 于 2016-3-22 06:07 编辑

板上有两片DDR3芯片：

DDR3的控制信号：

DDR3的初始化可以在gel文件中进行，也可以使用C程序进行初始化。DDR3的基地址在手册中是0x21000000。

在gel文件中的宏定义：

在cmd文件中也有相同的空间分配。

DDR3各寄存器的偏移地址如下的定义：DDR3时钟在Init_Pll2函数中，初始化在ddr3_setup_auto_lvl_1333()函数。

STK_Memory_Performance例程：而对于使用C文件进行初始化的DDR程序，使用的主要函数是void KeyStone_DDR_init(floatref_clock_MHz, unsigned int DDR_PLLM, unsignedint DDR_PLLD, DDR_ECC_Config * ecc_cfg)对于DDR3的初始化无非也是寄存器的配置，那么DDR3的寄存器有如下几个，其中也有它们的偏移地址，没有写出的还有61个CONFIG寄存器：

在这个函数中判断了芯片的型号，主要使用的函数是C6657的DDR3初始化程序，这两个芯片对于DDR3的初始化是一样的，而且是pin2pin的。 C6657_EVM_DDR_Init(DDR_Clock_MHz,ecc_cfg);

void C6657_EVM_DDR_Init(float clock_MHz, DDR_ECC_Config * ecc_cfg)
{
CSL_BootCfgUnlockKicker();
/*Invert Clock Out*/
KeyStone_DDR_clock_phase_init(TRUE);
//initial vale for leveling
/*WRLVL_INIT_RATIO*/
gpBootCfgRegs->DDR3_CONFIG_REG[2] = 0x6C;
gpBootCfgRegs->DDR3_CONFIG_REG[3] = 0x6C;
gpBootCfgRegs->DDR3_CONFIG_REG[4] = 0x7A;
gpBootCfgRegs->DDR3_CONFIG_REG[5] = 0x73;
gpBootCfgRegs->DDR3_CONFIG_REG[6] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[7] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[8] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[9] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[10] = 0x5C;
/*GTLVL_INIT_RATIO*/
gpBootCfgRegs->DDR3_CONFIG_REG[14] = 0xB0;
gpBootCfgRegs->DDR3_CONFIG_REG[15] = 0xB0;
gpBootCfgRegs->DDR3_CONFIG_REG[16] = 0xBD;
gpBootCfgRegs->DDR3_CONFIG_REG[17] = 0xC3;
gpBootCfgRegs->DDR3_CONFIG_REG[18] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[19] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[20] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[21] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[22] = 0xA4;
/*the PHY_RESET is pulsed (0 -> 1 -> 0) to latch these
leveling configuration values into the PHY logic.*/
KeyStone_DDR_latch_leveling_configuration ();
/*Drives CKE low.
This is a JEDEC requirement that we have 500us delay between reset de-assert
and cke assert and then program the correct refresh rate
The DDR internal clock is divide by 16 before SDCFG write*/
gpDDR_regs->SDRAM_REF_CTRL = CSL_EMIF4F_SDRAM_REF_CTRL_REG_INITREF_DIS_MASK
|(unsigned int)(500.f*clock_MHz/16.f);
gpDDR_regs->SDRAM_TIM_1 =
((unsigned int)(13.75*clock_MHz/1000.f-0.0001f)<
((unsigned int)(13.75*clock_MHz/1000.f-0.0001f)<
((unsigned int)(15*clock_MHz/1000.f-0.0001f)<
((unsigned int)(35*clock_MHz/1000.f-0.0001f)<
((unsigned int)(48.75*clock_MHz/1000.f-0.0001f)<
((unsigned int)(5*clock_MHz/4000.f-0.0001f)<
((unsigned int)(7.5*clock_MHz/1000.f-0.0001f)<
gpDDR_regs->SDRAM_TIM_2 =
((unsigned int)(6*clock_MHz/1000.f-0.0001f)<
((unsigned int)(170*clock_MHz/1000.f-0.0001f)<
((512-1)<
((unsigned int)(7.5*clock_MHz/1000.f-0.0001f)<
((unsigned int)(5*clock_MHz/1000.f-0.0001f)<
gpDDR_regs->SDRAM_TIM_3 =
(5<
((5)<
((unsigned int)(5*clock_MHz/1000.f+0.9999f)<
((64-1)<
((unsigned int)(160*clock_MHz/1000.f-0.0001f)<
(15<
gpDDR_regs->DDR_PHY_CTRL_1 = 0x00100100|
(13<
gpDDR_regs->ZQ_CONFIG =
((0)<
((1)<
((1)<
((1)<
((512/256-1)<
((256/64-1)<
/*interval between ZQCS commands = 0.5%/((TSens x Tdriftrate) + (VSens x Vdriftrate))
=0.5%/((max (dRTTdT, dRONdTM) x Tdriftrate in C/second) + (max(dRTTdV, dRONdVM) x Vdriftrate in mV/second))
this time need be converted to refresh period number*/
(((unsigned int)(1000000000*0.5/(1.5*1.2+0.15*15))/(64000000/8192))
<
/*map priority 0,1,2,3 to COS0,
map priority 3,5,6,7 to COS1*/
gpDDR_regs->PRI_COS_MAP =
((1)<
((1)<
((1)<
((1)<
((1)<
((0)<
((0)<
((0)<
((0)<
/*master based COS map is disabled*/
gpDDR_regs->MSTID_COS_1_MAP= 0;
gpDDR_regs->MSTID_COS_2_MAP= 0;
/*LAT_CONFIG*/
gpDDR_regs->VBUSM_CONFIG=
(8<
(16<
(32<
/*Read Write Execution Threshold*/
gpDDR_regs->RD_WR_EXEC_THRSH=
((1024/8/8-1)<
|((512/8/8-1)<
KeyStone_DDR_ECC_init(ecc_cfg);
/* enables DRAM configuration. It still has the refresh interval
programmed to the longer number needed during DRAM initialization.*/
gpDDR_regs->SDRAM_REF_CTRL = (unsigned int)(500.f*clock_MHz/16.f);
gpDDR_regs->SDRAM_CONFIG =
(3<
(0<
(DDR_TERM_RZQ_OVER_2<
(DDR_DYN_ODT_OVER_2<
(0<
(SDRAM_DRIVE_RZQ_OVER_7<
(DDR_CWL_8<
(DDR_BUS_WIDTH_32<
(DDR_CL_11<
(DDR_ROW_SIZE_14_BIT<
(DDR_BANK_NUM_8<
(0<
(DDR_PAGE_SIZE_10_BIT_1024_WORD<
TSC_delay_us(600); //Wait 600us for HW init to complete
// gpDDR_regs->SDRAM_REF_CTRL = 64000000/8192/(1000/clock_MHz);
gpDDR_regs->SDRAM_REF_CTRL = (unsigned int)64000.f*clock_MHz/8192.f;
KeyStone_DDR_full_leveling();
KeyStone_DDR_read_incremental_leveling(100);
}