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中间带了按键消抖,根据特权老师教学编的,跟老师代码不一样的地方在,左移,右移控制上
module key_filter( clk,rst_n, led, sw1, sw2, sw3 ); input clk; input rst_n; input sw1, sw2, sw3; output [3:0] led; reg led_dir; //1'b1左移 reg led_on; //1'b0停 //--------------------------------------------------------- reg [23:0] cnt; always @(posedge clk or negedge rst_n) if(!rst_n) cnt <= 24'd0; //else if(cnt == 24'hfff_fff) //cnt <= 24'd0; else cnt <= cnt + 1'b1; //------------------------------------------------------------ reg [3:0] led_r; // initial led_r <= 4'b1110; // initial led_on <= 1'b0; always @(posedge clk or negedge rst_n) if(!rst_n) begin led_r <=4'b1110; end else if(cnt == 24'hfff_fff && led_on) begin if(led_dir) begin led_r[3:1] <= led_r[2:0]; //led灯左移 led_r [0] <= led_r[3]; end else begin led_r[2:0] <= led_r[3:1]; //led灯又移 led_r [3] <= led_r[0]; end end assign led = led_r; //----------------------------------------------------------------------------------- reg [2:0] key_bw; always @(posedge clk or negedge rst_n) if(!rst_n) key_bw <= 3'b111; else key_bw <= {sw3, sw2, sw1}; reg [2:0] key_bw_r; always @(posedge clk or negedge rst_n) if(!rst_n) key_bw_r <= 3'b111; else key_bw_r <= key_bw; wire [2:0] key_en = key_bw_r & (~key_bw); //------------------------------------------------------------------- //计数器 reg [19:0] cnta; always @(posedge clk or negedge rst_n) if(!rst_n) cnta <= 20'd0; else if(key_en) cnta <= 20'd0; else cnta <= cnta + 1'b1; //---------------------------------------------------------------------- reg [2:0] key_ew; always @(posedge clk or negedge rst_n) if(!rst_n) key_ew <= 3'b111; else if(cnta == 20'hfffff) key_ew <= {sw3, sw2, sw1}; reg [2:0] key_ew_r; always @(posedge clk or negedge rst_n) if(!rst_n) key_ew_r <= 3'b111; else key_ew_r <= key_ew; wire [2:0] led_ctrl = key_ew_r & (~key_ew); //---------------------------------------------------------------- always @(posedge clk or negedge rst_n) if(!rst_n) begin led_on <= 1'b0; led_dir <= 1'b0; end else begin if(led_ctrl[0]) led_on <= ~led_on; if(led_ctrl[1]) led_dir <= 1'b0; if(led_ctrl[2]) led_dir <= 1'b1; end endmodule
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reg[3:0] led_r;
always @(posedge clk or negedge rst_n) if(!rst_n) led_r <= 4'b0001; else if(cnt24 == 24'hffffff && led_on) begin if(led_dir) led_r <= {led_r[0],led_r[3:1]}; //left else led_r <= {led_r[2:0],led_r[3]}; //right end assign led = led_r; 这是特权老师移位代码 |
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