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写了一个74HC595驱动 Modelsim 仿真出了正常波形 上板后没有反应 求助如何解决?
Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "sclk" is stuck at GND Warning (13410): Pin "lclk" is stuck at GND Warning (13410): Pin "s_data" is stuck at GND Warning: Design contains 2 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "clk" Warning (15610): No output dependent on input pin "rst_n" Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Warning: timing characteristics of device EP4CE15F17C8 are preliminary Warning: Timing characteristics of device EP4CE15F17C8 are preliminary Warning: Timing characteristics of device EP4CE15F17C8 are preliminary 代码如下 module led_drive( clk , rst_n , led_data, sclk , lclk , s_data ); //参数定义 parameter DATA_W = 8; //输入信号定义 input clk ; input rst_n ; input[DATA_W-1:0] led_data; //输出信号定义 output sclk ; output lclk ; output s_data ; wire sclk; wire lclk; wire s_data; //中间信号定义 reg state_c; reg state_n; reg[1:0] cnt; reg[3:0] sclk_cnt; wire update_flag; reg[DATA_W-1:0] led_data_r; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin state_c <= 1'b0; end else begin state_c <= state_n; end end always @(*)begin case(state_c) 0:begin if(update_flag) state_n = 1; else state_n = 0; end 1:begin if(sclk_cnt==4'd8 && cnt==2'd3) state_n = 0; else state_n = 1; end default:begin state_n = 0; end endcase end assign sclk = (cnt<2'd2)?1'b0:1'b1; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin cnt <= 1'b0; end else if(state_c)begin if(cnt==2'd3) cnt <= 1'b0; else cnt <= cnt + 1'b1; end end assign update_flag = (led_data_r!=led_data); always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin led_data_r <= 7'd0; end else begin led_data_r <= led_data; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin sclk_cnt <= 0; end else if(cnt==3)begin if(sclk_cnt==4'd8) sclk_cnt <= 4'd0; else sclk_cnt <= sclk_cnt + 1'b1; end end assign lclk = (state_c && sclk_cnt==4'd8)?1'b1:1'b0; assign s_data = (state_c && sclk_cnt<4'd8)?led_data[3'd7-sclk_cnt]:1'b0; endmodule |
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