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本帖最后由 lovely129 于 2014-7-3 17:28 编辑
本人新手，这是书上的例子，怎么会编译不成功？ library ieee; use std_logic_1164.all; entity chop8_1 is port(d,rst,clk: in bit; q: out bit); end chop8_1; architecture chop of chop8_1 is type state is (zero,one,two,three); signal pr_state, nx_state: state; begin --lower section-- process(clk,rst) begin if (rst='1') then pr_state<=zero; elsif (clk'event and clk='1') then pr_state<=nx_state; end if; end process; --upper section-- process(pr_state,d) begin case pr_state is when zero=> q<='0'; if (d='1') then nx_state<=one; else nx_state<=zero; end if; when one=> q<='0'; if (d='1') then nx_state<=two; else nx_state<=zero; end if; when two=> q<='0'; if (d='1') then nx_state<=three; else nx_state<=zero; end if; when three=> q<='1'; if (d='0') then nx_state<=zero; else nx_state<=three; end if; end case; end process; end chop; Error (10482): VHDL error at chop8_1.vhd(2): object "std_logic_1164" is used but not declared Error (10800): VHDL error at chop8_1.vhd(2): selected name in use clause is not an expanded name 
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淘帖
十分感谢！