library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; port(clk,rst:in std_logic; q:out std_logic_vector(15 downto 0); ); end cnt2249; architecture behave of cnt2249 is signal tho,hun,ten,one:std_logic_vector(3downto 0); begin process(clk,rst) begin if rst=’1’ then tho<=”0000”;hun<=”0000”,ten<=”0000”;one<=”0000”; elsif clk’eventand clk=’1’ then if tho=2 and hun=2 and ten=4 and one=9 then tho<=”0000”;hun<=”0000”,ten<=”0000”;one<=”0000”; elsif hun=9 and ten=9 and one=9 then hun<=”0000”,ten<=”0000”;one<=”0000”;tho<=tho+1; elsif ten=9 andone=9 then ten<=”0000”;one<=”0000”;hun<=hun+1; elsif one=9 then one<=”0000”;ten<=ten+1; else one<=one+1; end if; end if; end process; q<=tho&hun&ten&one; end behav;
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