大家帮我看看这个VHDL100进制计数器有没有问题

仿真

仿真时候就是不对。。都乱了。。library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt100 is
port(clk:in std_logic;
      q:out std_logic_vector(7 downto 0);
c:out std_logic);
end cnt100;
architecture one of cnt100 is
signal qa:std_logic_vector(3 downto 0);
signal qb:std_logic_vector(3 downto 0);
signal cin:std_logic;
begin
q(3 downto 0)<=qa;
q(7 downto 4)<=qb;
process(clk)
begin
   if clk'event and clk='1' then
   if qa=9 then qa<="0000";cin<='1';
else qa<=qa+1;cin<='0';
end if;
end if;
end process;
process(clk,cin)
begin
      if clk'event and clk='1' then
      if (qb=9 and qa=9) then qb<="0000";c<='1';
   else c<='0';
   end if;
   if cin='1' then qb<=qb+1;
   end if;
end if;
end process;
end one;

愤怒的呼呼 · 2013-11-15 23:37:46

把 if qa=9 then qa<="0000"改成if qa=8 then qa《=“0000”；试试吧

vvg · 2013-11-16 12:49:23

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vhdl is
port(clk:in std_logic;
            q:out std_logic_vector(7 downto 0);
                     c:out std_logic);
end vhdl;
architecture one of vhdl is
signal qa:std_logic_vector(3 downto 0);
signal qb:std_logic_vector(3 downto 0);
signal cin:std_logic;
begin
q(3 downto 0)<=qa;
      q(7 downto 4)<=qb;
process(clk,qa,qb)
      begin
         if clk'event and clk='1' then


if qb=9 and qa>9 then qa<="0000";
qb<="0000";
cin<='1';
elsif qa>9 then qb<=qb+'1';cin<='0';
else
   qa<=qa+'1';

end if;
end if;

      end process;
end one;

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大家帮我看看这个VHDL100进制计数器有没有问题

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