我这个程序能实现吗？本意是想让32为寄存器每四位乘以一.

module control_k(A,Q1,Q2,CLK);
input [31:0]A;
input CLK;
output[15:0]Q1,Q2;
wire[31:0]K;
wire[15:0]Q1,Q2;
wire [31:0] f;
wire[31:0] f0,f1,f2,f3,f4,f5,f6,f7;
wire[31:0] sum1,sum2,sum3,sum4,sum5;
reg [31:0]reg1,reg2,reg3,reg4,reg5,reg6,REG1,REG2,REG3,REG4,REG5,REG6,REG7;
parameter S=2147483648;
parameter MHz=25000000;
parameter s1=1;
parameter s2=10;
parameter s3=100;
parameter s4=1000;
parameter s5=10000;
parameter s6=100000;
parameter s7=1000000;
parameter s8=10000000;
assign f0=A[3:0]*s1;
assign f1=A[7:3]*s2;
assign f2=A[11:8]*s3;
assign f3=A[15:12]*s4;
assign f4=A[19:16]*s5;
assign f5=A[23:20]*s6;
assign f6=A[27:24]*s7;
assign f7=A[31:28]*s8;
assign sum1=REG1+REG2;
assign sum2=REG3+REG4;
assign sum3=REG5+REG6;
assign sum4=reg1+REG7;
assign sum5=reg2+reg3;
assign f=reg4+reg5;
always@(posedge CLK)
begin
REG1<=f0;
REG2<=f2;
REG3<=f3;
REG4<=f4;
REG5<=f5;
REG6<=f6;
REG7<=f7;

reg1<=sum1;
reg2<=sum2;
reg3<=sum3;
reg4<=sum4;
reg5<=sum5;
reg6<=f;
end


assign K=(f*S/MHz);
assign Q2=K[31:16];
assign Q1=K[15:0];


endmodule