这问题没人解决，元芳你怎么看？

通信

用的 epm240 cpld
假如屏蔽掉pwm计数进程  就没有这些警告和错误了。
哪位大神知道，要想不屏蔽这些进程，还能消除警告和错误该怎么办啊？

序代码如下：

//本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在
//PC机上安装一个串口调试工具来验证程序的功能。
//程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控
//制器，10个bit是1位起始位，8个数据位，1个结束
//位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实
//现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是
//9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间
//划分为8个时隙以使通信同步.
//字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制
module sci(clk,rst,rxd,dir,pwm1,pwm2,pwm3,pwm4);
///////////////串口数值
input clk,rst;
output pwm1,pwm2,pwm3,pwm4;
output[3:0] dir;
input rxd;//串行数据接收端
reg[15:0] div_reg;//分频计数器，分频值由波特率决定。分频后得到频率8倍波特率的时?
reg[2:0]  div8_rec_reg;//该寄存器的计数值对应接收时当前位于的时隙数
reg[3:0] state_rec;//接受状态寄存器
reg clkbaud_rec;//以波特率为频率的接受使能信号
reg clkbaud8x;//以8倍波特率为频率的时钟，它的作用是将发送或接受一个bit的时钟周期分为8个时隙
reg recstart;//开始接受标志
reg recstart_last;//开始接受标志暂存值
reg[1:0] recstart_cnt;//起始时钟计数
reg rxd_reg1;//接收寄存器1
reg rxd_reg2;//接收寄存器2，因为接收数据为异步信号，故用两级缓存
reg[7:0] rxd_buf;//接受数据缓存
reg[4:0] count;//按此数接收数据分配
reg write=0;//数据接收完毕可以发送脉冲标志
reg[15:0] div_1sci;////低八位
reg[15:0] div_2sci;////高八位
reg[15:0] div_3sci;
reg[15:0] div_4sci;
reg[15:0] pwm_1sci;
reg[15:0] pwm_2sci;
reg[15:0] pwm_3sci;
reg[15:0] pwm_4sci;
/////////////////pwm计数
reg[3:0] dir=0;//接收到的方向信号
reg[15:0] div_1cnt;//分频数
reg[15:0] div_2cnt;
reg[15:0] div_3cnt;
reg[15:0] div_4cnt;
reg[15:0] pwm_1cnt;//脉冲数
reg[15:0] pwm_2cnt;
reg[15:0] pwm_3cnt;
reg[15:0] pwm_4cnt;
reg[7:0] cnt;//1M基准脉冲计数器
reg[15:0] div_1;//分频计数器
reg[15:0] div_2;
reg[15:0] div_3;
reg[15:0] div_4;
reg clk1mhz;//1mhz的基准脉冲
reg clkdiv1;//pwm1
reg clkdiv2;//pwm2
reg clkdiv3;//pwm3
reg clkdiv4;//pwm4
reg link1,link2,link3,link4;//pwm输出的使能
parameter div_par=16'h145;//分频参数，其值由对应的波特率计算而得，按此参数分频的时钟频率是波倍特率的8
                  //倍，此处值对应9600的波特率，即分频出的时钟频率是9600*8  (CLK  50M)
assign pwm1=(link1==1)?clkdiv1:1'b0;
assign pwm2=(link2==1)?clkdiv2:1'b0;
assign pwm3=(link3==1)?clkdiv3:1'b0;
assign pwm4=(link4==1)?clkdiv4:1'b0;
/**************串口通信*****************/
always@(posedge clk )//50m进行325分频在进行二分频,分频得到8倍波特率的时钟
begin
if(!rst)
  begin
div_reg<=0;
clkbaud8x<=0;
  end
else
begin
if(div_reg==div_par-1)
begin
   div_reg<=0;
   clkbaud8x<=~clkbaud8x;
end
else
div_reg<=div_reg+1'b1;
end
end
always@(posedge clkbaud8x,negedge rst)//对时隙计数
begin
if(!rst)
  div8_rec_reg<=0;
else if(recstart)//接收开始标志
  div8_rec_reg<=div8_rec_reg+1'b1;//接收开始后，时隙数在8倍波特率的时钟下加1循环
end
always@(div8_rec_reg)//在第7个时隙，接收使能信号有效，将数据打入
begin
if(div8_rec_reg==7)
  clkbaud_rec=1;
else
  clkbaud_rec=0;
end
always@(posedge clkbaud8x,negedge rst)//接受PC机的数据
begin
if(!rst)
  begin
rxd_reg1<=0;
rxd_reg2<=0;
rxd_buf<=0;
state_rec<=0;
recstart<=0;
recstart_last<=0;
recstart_cnt<=0;
  end

else
  begin
if(state_rec==0)
   begin
   rxd_reg1<=rxd;
   rxd_reg2<=rxd_reg1;
   if(recstart_last==1)
   begin
   if(recstart_cnt==3)//连续4个低电平表示有效地起始位
      begin
      recstart_cnt<=0;
      recstart_last<=0;
      state_rec<=state_rec+1'b1;
      end
   else
      recstart_cnt<=recstart_cnt+1'b1;
   end
   else if(!rxd_reg1 && rxd_reg2) //检测到起始位的下降沿，进入接受状态
   begin
   recstart_last<=1;
   recstart<=1;
   end
   end
else if(state_rec>=1&&state_rec<=8) //先低位后高位
   begin
   if(clkbaud_rec)
   begin
   rxd_buf[7]<=rxd_reg2;
   rxd_buf[6:0]<=rxd_buf[7:1];//右移1bit
   state_rec<=state_rec+1'b1;
   end
   end
else if(state_rec==9)
   begin
   if(clkbaud_rec)
   begin
   state_rec<=0;
   recstart<=0;
   end
   end
  end
end
always@(posedge clkbaud8x,negedge rst)//接受PC机的数据
begin
if(!rst)
  count<=0;
else if(count==17)//一组新数据发送完毕
  begin
count<=0;
write<=1'b1;//接受到的数据发给pwm计数器
  end
else
  begin
write<=0;
if(state_rec==9)
count<=count+1'b1;
  end
end
/*****************PWM*****************/
always@(count) //将接受的数据转化为分频数和脉冲数
begin
case (count)
  5'b00001://1
div_1sci[7:0]<=rxd_buf;//低八位
  5'b00010://2
div_1sci[15:8]<=rxd_buf;//高八位
  5'b00011://3
div_2sci[7:0]<=rxd_buf;
  5'b00100://4
div_2sci[15:8]<=rxd_buf;
  5'b00101://5
div_3sci[7:0]<=rxd_buf;
  5'b00110://6
div_3sci[15:8]<=rxd_buf;
  5'b00111://7
div_4sci[7:0]<=rxd_buf;
  5'b01000://8
div_4sci[15:8]<=rxd_buf;
  5'b01001://9
pwm_1sci[7:0]<=rxd_buf;
  5'b01010://10
pwm_1sci[15:8]<=rxd_buf;
  5'b01011://11
pwm_2sci[7:0]<=rxd_buf;
  5'b01100://12
pwm_2sci[15:8]<=rxd_buf;
  5'b01101://13
pwm_3sci[7:0]<=rxd_buf;
  5'b01110://14
pwm_3sci[15:8]<=rxd_buf;
  5'b01111://15
pwm_4sci[7:0]<=rxd_buf;
  5'b10000://16
pwm_4sci[15:8]<=rxd_buf;
  5'b10001://17
dir<=rxd_buf[3:0];//低四位为方向信号
  default:
begin
div_1sci<=0;
div_2sci<=0;
div_3sci<=0;
div_4sci<=0;

pwm_1sci<=0;
pwm_2sci<=0;
pwm_3sci<=0;
pwm_4sci<=0;
end
endcase
end
/**************产生基准脉冲********************/
always@(posedge clk )//50m进行50分频成1m基准脉冲
begin
if(!rst)
  begin
cnt<=0;
clk1mhz<=0;
  end
else begin
  if(cnt==24)//(50>>1)-1
begin
cnt<=0;
clk1mhz<=~clk1mhz;
end
  else
cnt<=cnt+1'b1;
end
end
/**************产生pwm*******************/
always@(posedge clk1mhz,negedge rst)//分频产生pwm1
begin
if(!rst)
  clkdiv1<=0;
else if(div_1==(div_1sci>>1)-1)//产生占空比50%100的脉冲
  begin
div_1<=0;
clkdiv1<=~clkdiv1;
  end
else
  div_1<=div_1+1'b1;
end
/////////////
always@(posedge clk1mhz,negedge rst)//分频产生pwm2
begin
if(!rst)
  clkdiv2<=0;
else if(div_2==(div_2sci>>1)-1)
  begin
div_2<=0;
clkdiv2<=~clkdiv2;
  end
else
  div_2<=div_2+1'b1;
end
/////////////
always@(posedge clk1mhz,negedge rst)//分频产生pwm3
begin
if(!rst)
  clkdiv3<=0;
else if(div_3==(div_3sci>>1)-1)
  begin
div_3<=0;
clkdiv3<=~clkdiv3;
  end
else
  div_3<=div_3+1'b1;
end
/////////////
always@(posedge clk1mhz,negedge rst)//分频产生pwm4
begin
if(!rst)
  clkdiv4<=0;
else if(div_4==(div_4sci>>1)-1)
  begin
div_4<=0;
clkdiv4<=~clkdiv4;
  end
else
  div_4<=div_4+1'b1;
end
/*****************pwm计数**************/
always@(posedge clkdiv1,posedge write,negedge rst)//pwm1计数
begin
if(!rst)
  begin
link1<=0;
pwm_1cnt<=0;
  end
else if(write)
  pwm_1cnt<=pwm_1sci;
else if(pwm_1cnt==0)
  link1<=0;
else
  begin
pwm_1cnt<=pwm_1cnt-1'b1;//脉冲发送完毕计数器减到零停止计数
link1<=1;
  end
end
always@(posedge clkdiv2,posedge write,negedge rst)//pwm2计数
begin
if(!rst)
  begin
link2<=0;
pwm_2cnt<=0;
  end
else if(write)
  pwm_2cnt<=pwm_2sci;
else if(pwm_2cnt==0)
  link2<=0;
else
  begin
pwm_2cnt<=pwm_2cnt-1'b1;
link2<=1;
  end
end
///////////
always@(posedge clkdiv3,posedge write,negedge rst)//pwm3计数
begin
if(!rst)
  begin
link3<=0;
pwm_3cnt<=0;
  end
else if(write)
  pwm_3cnt<=pwm_3sci;
else if(pwm_3cnt==0)
  link3<=0;
else
  begin
pwm_3cnt<=pwm_3cnt-1'b1;
link3<=1;
  end
end
////////////
always@(posedge clkdiv4,posedge write,negedge rst)//pwm4计数
begin
if(!rst)
  begin
link4<=0;
pwm_4cnt<=0;
  end
else if(write)
  pwm_4cnt<=pwm_4sci;
else if(pwm_4cnt==0)
  link4<=0;
else
  begin
pwm_4cnt<=pwm_4cnt-1'b1;
link4<=1;
  end
end
endmodule

警告如下：
Warning: Latch div_1sci[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[3] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[4] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[5] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[6] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[7] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[8] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[9] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[10] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[11] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[12] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[13] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[14] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch div_1sci[15] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch pwm_1sci[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch pwm_1sci[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]
Warning: Latch pwm_1sci[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal count[4]

错误：
Error: Design contains 636 blocks of type logic cell.  However, device contains only 240.
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Error: Can't fit design in device
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file C:/altera/90sp2/quartus/verilogproject/testsci1/sci.fit.smsg
Error: Quartus II Fitter was unsuccessful. 2 errors, 2 warnings
Error: Peak virtual memory: 190 megabytes
Error: Processing ended: Sun Nov 04 13:07:27 2012
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 276 warnings