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本帖最后由 eehome 于 2013-1-5 09:55 编辑
有用rs232实现传输8位数据的程序,我就想把它改一改成为传输32位数据的程序,可是改了之后,发现传输不了数据,求大神帮忙分析一下。(用verilog语言) 我就把输入的程序复制4次,分别命名为U0,U1,U2,U3,每个Ui在接收完数据后,都有个结束信号d,下一个接收程序在接收到d信号的下降沿后,就启动开始接收数据。U4接受完数据后,就把值送给寄存器,并把d送给发送模块,发送模块接收到d的下降沿后,就开始发送数据。我在发送模块里设了个变量m,当M<4时,继续发送,当M>=4时,就结束发送。 |
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11个回答
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楼主 你把待发送的数据分成 四组八位 的不就可以了么,每一组得要包含起始位 结束位。在你的程序里面 没有发现起始跟结束位,这样是不满足uart传输的规定的。232口无法识别。
最佳答案
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把源代码贴上来,看一看!
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module uart (clk,rst_n,rs232_rx,rs232_tx,b,a,e,k);
input clk,rst_n,rs232_rx; output rs232_tx; output b,a,e,k; wire clk_bps_r,bps_start_r,d_r,clk_bps_t,bps_start_t; wire [31:0] A; wire rx_int; speed_select rs(clk,rst_n,bps_start_r,clk_bps_r); my_uart_rx r(clk,rst_n,rs232_rx,clk_bps_r,bps_start_r,d_r,A,a,k); speed_select ts(clk,rst_n,bps_start_t,clk_bps_t); my_uart_tx t(clk,rst_n,A,d_r,rs232_tx,clk_bps_t,bps_start_t,e); assign b=clk_bps_t; endmodule module my_uart_rx( clk,rst_n, rs232_rx, clk_bps,bps_start,done, A,b,k ); input clk; input rst_n; input rs232_rx; input clk_bps; output bps_start; output done; output [31:0] A; output b; reg b,k; output k; reg rs232_rx0,rs232_rx1,rs232_rx2; wire neg_rs232_rx; reg [7:0] a[3:0]; reg [2:0] m; reg done; always @ (posedge clk or negedge rst_n) begin if(!rst_n) begin rs232_rx0 <= 1'b0; rs232_rx1 <= 1'b0; rs232_rx2 <= 1'b0; end else begin rs232_rx0 <= rs232_rx; rs232_rx1 <= rs232_rx0; rs232_rx2 <= rs232_rx1; end end assign neg_rs232_rx = rs232_rx2 & rs232_rx1 & ~rs232_rx0; reg bps_start_r; reg[3:0] num; reg rx_int; always @ (posedge clk or negedge rst_n) if(!rst_n) begin bps_start_r <= 1'bz; rx_int<=1'b0; b<=1'b0; end else if(neg_rs232_rx) begin bps_start_r <= 1'b1; rx_int<=1'b1; b<=1'b1; end else if(m>=4) begin bps_start_r <= 1'b0; rx_int<=1'b0; b<=1'b0; end assign bps_start = bps_start_r; reg[7:0] rx_temp_data; always @ (posedge clk or negedge rst_n) if(!rst_n) begin rx_temp_data <= 8'd0; num <= 4'd0; m<=3'b0; done<=1'b0; k<=1'b0; a[3]<=8'b0; a[2]<=8'b0; a[1]<=8'b0; a[0]<=8'b0; end else if(rx_int) begin if(clk_bps) begin num <= num+1'b1; case (num) 4'd1: rx_temp_data[0] <= rs232_rx; //锁存第0bit 4'd2: rx_temp_data[1] <= rs232_rx; //锁存第1bit 4'd3: rx_temp_data[2] <= rs232_rx; //锁存第2bit 4'd4: rx_temp_data[3] <= rs232_rx; //锁存第3bit 4'd5: rx_temp_data[4] <= rs232_rx; //锁存第4bit 4'd6: rx_temp_data[5] <= rs232_rx; //锁存第5bit 4'd7: rx_temp_data[6] <= rs232_rx; //锁存第6bit 4'd8: rx_temp_data[7] <= rs232_rx; //锁存第7bit default: ; endcase end else if(num == 4'd12) begin num <= 4'd0; if(m>=4) begin done<=1'b1; k<=1'b1; m<=3'b0; end else begin a[m]<=rx_temp_data; m<=m+1'b1; end end end assign A={a[3],a[2],a[1],a[0]}; endmodule module my_uart_tx( clk,rst_n, C,rx_int,rs232_tx, clk_bps,bps_start,e ); input clk; input rst_n; input clk_bps; input [31:0] C; input rx_int; output rs232_tx; output bps_start; output e; reg rx_int0,rx_int1,rx_int2; wire neg_rx_int; reg e; always @ (posedge clk or negedge rst_n) begin if(!rst_n) begin rx_int0 <= 1'b0; rx_int1 <= 1'b0; rx_int2 <= 1'b0; end else begin rx_int0 <= rx_int; rx_int1 <= rx_int0; rx_int2 <= rx_int1; end end assign neg_rx_int = rx_int0 & ~rx_int1 & ~rx_int2; reg[39:0] tx_data; //待发送数据的寄存器 reg bps_start_r; reg tx_en; //发送数据使能信号,高有效 reg[5:0] num; always @ (posedge clk or negedge rst_n) begin if(!rst_n) begin bps_start_r <= 1'bz; tx_en <= 1'b0; tx_data <= 8'd0; e<=1'b0; end else if(neg_rx_int) begin //接收数据完毕,准回去 bps_start_r <= 1'b1; tx_data <= {1'b1,C[31:24],1'b0,1'b1,C[23:16],1'b0,1'b1,C[15:8],1'b0,1'b1,C[7:0],1'b0}; //把接收据寄存器 tx_en <= 1'b1; //进入发态中 e<=1'b1; end else if(num>=6'd40) begin //数据发送完成,复位 bps_start_r <= 1'b0; tx_en <= 1'b0; e<=1'b0; end end assign bps_start = bps_start_r; reg rs232_tx_r; always @ (posedge clk or negedge rst_n) begin if(!rst_n) begin num <= 6'd0; rs232_tx_r <= 1'b1; end else if(tx_en) begin if(clk_bps) begin num <= num+1'b1; case (num) 6'd0: rs232_tx_r <= tx_data[0]; //发送起始位 6'd1: rs232_tx_r <= tx_data[1]; //发送bit0 6'd2: rs232_tx_r <= tx_data[2]; //发送bit1 6'd3: rs232_tx_r <= tx_data[3]; //发送bit2 6'd4: rs232_tx_r <= tx_data[4]; //发送bit3 6'd5: rs232_tx_r <= tx_data[5]; //发送bit4 6'd6: rs232_tx_r <= tx_data[6]; //发送bit5 6'd7: rs232_tx_r <= tx_data[7]; //发送bit6 6'd8: rs232_tx_r <= tx_data[8]; //发送bit7 6'd9: rs232_tx_r <= tx_data[9]; //发送8 6'd10: rs232_tx_r <= tx_data[10]; //发送bit0 6'd11: rs232_tx_r <= tx_data[11]; //发送bit1 6'd12: rs232_tx_r <= tx_data[12]; //发送bit2 6'd13: rs232_tx_r <= tx_data[13]; //发送bit3 6'd14: rs232_tx_r <= tx_data[14]; //发送bit4 6'd15: rs232_tx_r <= tx_data[15]; //发送bit5 6'd16: rs232_tx_r <= tx_data[16]; //发送bit6 6'd17: rs232_tx_r <= tx_data[17]; //发送bit7//发送结束位 6'd18: rs232_tx_r <= tx_data[18]; //发送起始位 6'd19: rs232_tx_r <= tx_data[19]; //发送bit0 6'd20: rs232_tx_r <= tx_data[20]; //发送bit1 6'd21: rs232_tx_r <= tx_data[21]; //发送bit2 6'd22: rs232_tx_r <= tx_data[22]; //发送bit3 6'd23: rs232_tx_r <= tx_data[23]; //发送bit4 6'd24: rs232_tx_r <= tx_data[24]; //发送bit5 6'd25: rs232_tx_r <= tx_data[25]; //发送bit6 6'd26: rs232_tx_r <= tx_data[26]; //发送bit7 6'd27: rs232_tx_r <= tx_data[27]; //发送8 6'd28: rs232_tx_r <= tx_data[28]; //发送bit0 6'd29: rs232_tx_r <= tx_data[29]; //发送bit1 6'd30: rs232_tx_r <= tx_data[30]; //发送bit2 6'd31: rs232_tx_r <= tx_data[31]; //发送bit3 6'd32: rs232_tx_r <= tx_data[32]; //发送bit4 6'd33: rs232_tx_r <= tx_data[33]; //发送bit5 6'd34: rs232_tx_r <= tx_data[34]; //发送bit6 6'd35: rs232_tx_r <= tx_data[35]; 6'd36: rs232_tx_r <= tx_data[36]; //发送8 6'd37: rs232_tx_r <= tx_data[37]; //发送bit0 6'd38: rs232_tx_r <= tx_data[38]; //发送bit1 6'd39: rs232_tx_r <= tx_data[39]; //发送bit2 default: rs232_tx_r <= 1'b1; endcase end else if(num==6'd40) num <= 6'd0; //复位 end end assign rs232_tx = rs232_tx_r; endmodule module speed_select( clk,rst_n, bps_start,clk_bps ); input clk; input rst_n; input bps_start; output clk_bps; parameter bps9600 = 5207, //波特率为9600bps bps19200 = 2603, //波特率19200bps bps38400 = 1301, //波特率38400bps bps57600 = 867, //波特率57600bps bps115200 = 433; //波特率115200bps parameter bps9600_2 = 2603, bps19200_2 = 1301, bps38400_2 = 650, bps57600_2 = 433, bps115200_2 = 216; `define BPS_PARA 2603 //波特率为9600时的分频计数值 `define BPS_PARA_2 1301 //波特率为9600时的分频计数值的一半,用于数据采样 reg[12:0] cnt; //分频计数 reg clk_bps_r; //波特率时钟寄存器 //---------------------------------------------------------- reg[2:0] uart_ctrl; // uart波特率选择寄存器 //---------------------------------------------------------- always @ (posedge clk or negedge rst_n) if(!rst_n) cnt <= 13'd0; else if((cnt == `BPS_PARA) || !bps_start) cnt <= 13'd0; //波特率计数清零 else cnt <= cnt+1'b1; //波特率时钟计数启动 always @ (posedge clk or negedge rst_n) if(!rst_n) clk_bps_r <= 1'b0; else if(cnt == `BPS_PARA_2) clk_bps_r <= 1'b1; else clk_bps_r <= 1'b0; assign clk_bps = clk_bps_r; endmodule
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新手学习
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别啊,这代码不对,我是想求人帮我的,结果他让我把代码贴上来,就再也没人理我了
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你解决这个问题了吗?我要写一个连续发送16为数据的程序,但是只能连续发送就有问题。也不知道为什么,让我看看你改好的程序吧
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请问楼主解决了这个问题吗,我也是想通过FPGA串口发送32位的数据,可否给我指点一下呢,感激不尽,我邮箱major201@126.com,可不可以吧你修改好的跟我发一份呢
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我问一句,UART串口协议不是应该起始位为0,停止位为1吗。
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学习学习
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