RGB驱动测试
1、硬件连接原理
1.1 RGB LCD连接关系
file:///C:/Users/ADMINI~1/AppData/Local/Temp/msohtmlclip1/01/clip_image020.jpg
RGB-LCD驱动信号为3.3V,采用16位色565模式驱动,引脚分配关系如下表。 序号 | RGB-LCD | PIN | 1 | R3 | PIN75 | 2 | R4 | PIN74 | 3 | R5 | PIN73 | 4 | R6 | PIN72 | 5 | R7 | PIN71 | 6 | G2 | PIN70 | 7 | G3 | PIN69 | 8 | G4 | PIN68 | 9 | G5 | PIN57 | 10 | G6 | PIN56 | 11 | G7 | PIN55 | 12 | B3 | PIN54 | 13 | B4 | PIN53 | 14 | B5 | PIN51 | 15 | B6 | PIN42 | 16 | B7 | PIN41 | 17 | CLK | PIN35 | 18 | HSYNC | PIN40 | 19 | HVYNC | PIN34 | 20 | DEN | PIN33 | 21 | XR | PIN32 | 22 | YD | PIN31 | 23 | XL | PIN63 | 24 | YU | PIN50 |
1.2 Button连接关系
按键共有2个,也是1.8V
序号 | KEY | PIN | 1 | KEY1 | PIN3 | 2 | KEY2 | PIN4 |
1.3 时钟输入
有源晶振为27MHz,通过PIN52脚输入。
2、屏幕安装方法说明: LCD显示器为4.3寸,型号JST-4300QWA-V01,采用FPC-40-0.5mm的连接器,在LCD的排线上标有明确的标号1脚和40脚,这整好和 开发板上的FPC座的引脚对应。我们按照引脚的对应关系插入,扣好FPC连接器的黑色卡扣,排线就安装完成了。如下图所示
3、RGB屏驱动时序 包括两种驱动模式,分别为行、场同步模式,另一种是DE同步模式。在行、场同步模式时,要求数据使能信号DE为低电平;在DE同步模式时,行、场同步信号需要为高电平。 3.1 行、场同步模式
RGB显示器是逐行填充数据,填充一行后再填充下一行,直到整个屏幕的所有像素点都填充完成。如下图所示。
行扫描周期包括同步脉冲,显示后沿,实际有效像素,显示前沿。如下图所示,行扫描的频率是以像素点填充时钟为基础的。
场扫描周期同行扫描类似,同样包括同步脉冲,显示后沿,有效图像,显示前沿,所不同的是,场扫描频率是以行扫描周期为基础的,也就是说,扫描完一个行周期,才增加一个场扫描时钟。
3.2 DE同步模式
如图所示,只要DE信号有效,就填充整个显示区域,同时需要考虑增加显示后沿和显示前沿。 3.3 我们实际使用的屏幕的驱动时序
我们采用的4.3寸屏时序,如小表。
从表中我们可以获得驱动RGB所需的时序信息。
4、 RGB显示屏的驱动程序
4.1 顶层
- module TOP
- (
- input Reset_Button,
- input User_Button,
- input XTAL_IN,
- output LCD_CLK,
- output LCD_HYNC,
- output LCD_SYNC,
- output LCD_DEN,
- output [4:0] LCD_R,
- output [5:0] LCD_G,
- output [4:0] LCD_B
- );
- wire CLK_SYS;
- wire CLK_PIX;
- /*
- This program uses external crystal oscillator and PLL to generate 33.33mhz clock to the screen
- If you use our 4.3-inch screen, you need to modify the PLL parameters (tools - > IP core generator)
- to make CLK_ Pix is between 8-12mhz (according to the specification of the screen)
- */
- Gowin_rPLL chip_pll
- (
- .clkout(CLK_SYS), //output clkout //108M
- .clkoutd(CLK_PIX), //output clkoutd //9M
- .clkin(XTAL_IN) //input clkin
- );
- VGAMod D1
- (
- .CLK ( CLK_SYS ),
- .nRST ( Reset_Button),
- .PixelClk ( CLK_PIX ),
- .LCD_DE ( LCD_DEN ),
- .LCD_HSYNC ( LCD_HYNC ),
- .LCD_VSYNC ( LCD_SYNC ),
- .LCD_B ( LCD_B ),
- .LCD_G ( LCD_G ),
- .LCD_R ( LCD_R )
- );
- assign LCD_CLK = CLK_PIX;
- endmodule
复制代码
4.2 时钟
时钟采用系统提供的锁相环IP,输入时钟27MHz,输出有两组,一组为系统时钟108MHz,另一组为9Mhz,这个时钟是提供给RGB屏刷新使用。
点击确定后会在工程下面创建出锁相环的Verilog代码。 4.3 RGB条形驱动
其中的RGB驱动时序是按照前面介绍的行场扫描时序调整的
- module VGAMod
- (
- input CLK,
- input nRST,
- input PixelClk,
- output LCD_DE,
- output LCD_HSYNC,
- output LCD_VSYNC,
- output [4:0] LCD_B,
- output [5:0] LCD_G,
- output [4:0] LCD_R
- );
- reg [15:0] PixelCount;
- reg [15:0] LineCount;
- //pluse include in back pluse; t=pluse, sync act; t=bp, data act; t=bp+height, data end
- localparam V_BackPorch = 16'd12;
- localparam V_Pluse = 16'd11;
- localparam HightPixel = 16'd272;
- localparam V_FrontPorch= 16'd4;
-
- localparam H_BackPorch = 16'd43;
- localparam H_Pluse = 16'd10;
- localparam WidthPixel = 16'd480;
- localparam H_FrontPorch= 16'd4;
- localparam Width_bar = 35;
- reg [15:0] BarCount;
-
-
- localparam PixelForHS = WidthPixel + H_BackPorch + H_FrontPorch;
- localparam LineForVS = HightPixel + V_BackPorch + V_FrontPorch;
- always @( posedge PixelClk or negedge nRST )begin
- if( !nRST ) begin
- LineCount <= 16'b0;
- PixelCount <= 16'b0;
- end
- else if( PixelCount == PixelForHS ) begin
- PixelCount <= 16'b0;
- LineCount <= LineCount + 1'b1;
- end
- else if( LineCount == LineForVS ) begin
- LineCount <= 16'b0;
- PixelCount <= 16'b0;
- end
- else
- PixelCount <= PixelCount + 1'b1;
- end
- reg [9:0] Data_R;
- reg [9:0] Data_G;
- reg [9:0] Data_B;
- always @( posedge PixelClk or negedge nRST )begin
- if( !nRST ) begin
- Data_R <= 9'b0;
- Data_G <= 9'b0;
- Data_B <= 9'b0;
- BarCount <=9'd0;
- end
- else begin
- end
- end
- //注意这里HSYNC和VSYNC负极性
- assign LCD_HSYNC = (( PixelCount >= H_Pluse)&&( PixelCount <= (PixelForHS-H_FrontPorch))) ? 1'b0 : 1'b1;
- // assign LCD_VSYNC = ((( LineCount >= 0 )&&( LineCount <= (V_Pluse-1) )) ) ? 1'b1 : 1'b0; //这里不减一的话,图片底部会往下拖尾?
- assign LCD_VSYNC = ((( LineCount >= V_Pluse )&&( LineCount <= (LineForVS-0) )) ) ? 1'b0 : 1'b1;
- //assign FIFO_RST = (( PixelCount ==0)) ? 1'b1 : 1'b0; //留给主机H_BackPorch的时间进入中断,发送数据
- // assign LCD_HSYNC = 1'b0;
- // assign LCD_VSYNC = 1'b0;
- assign LCD_DE = ( ( PixelCount >= H_BackPorch )&&
- ( PixelCount <= PixelForHS-H_FrontPorch ) &&
- ( LineCount >= V_BackPorch ) &&
- ( LineCount <= LineForVS-V_FrontPorch-1 )) ? 1'b1 : 1'b0;
- // 这里不减一,会抖动
- assign LCD_R = (PixelCount
- (PixelCount<(Width_bar*(BarCount+1)) ? 5'b00001 :
- (PixelCount<(Width_bar*(BarCount+2)) ? 5'b00010 :
- (PixelCount<(Width_bar*(BarCount+3)) ? 5'b00100 :
- (PixelCount<(Width_bar*(BarCount+4)) ? 5'b01000 :
- (PixelCount<(Width_bar*(BarCount+5)) ? 5'b10000 : 5'b00000 )))));
- assign LCD_G =(PixelCount<(Width_bar*(BarCount+5)))? 6'b000000 :
- (PixelCount<(Width_bar*(BarCount+6)) ? 6'b000001 :
- (PixelCount<(Width_bar*(BarCount+7)) ? 6'b000010 :
- (PixelCount<(Width_bar*(BarCount+8)) ? 6'b000100 :
- (PixelCount<(Width_bar*(BarCount+9)) ? 6'b001000 :
- (PixelCount<(Width_bar*(BarCount+10)) ? 6'b010000 :
- (PixelCount<(Width_bar*(BarCount+11)) ? 6'b100000 : 6'b000000 ))))));
- assign LCD_B=(PixelCount<(Width_bar*(BarCount+11)))? 5'b00000 :
- (PixelCount<(Width_bar*(BarCount+12)) ? 5'b00001 :
- (PixelCount<(Width_bar*(BarCount+13)) ? 5'b00010 :
- (PixelCount<(Width_bar*(BarCount+14)) ? 5'b00100 :
- (PixelCount<(Width_bar*(BarCount+15)) ? 5'b01000 :
- (PixelCount<(Width_bar*(BarCount+16)) ? 5'b10000 : 5'b00000 )))));
- endmodule
复制代码
5、实际显示效果
|