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说明:本文适用于 RK3399 linux 4.4 内核系列SDK。硬件上,音频外部 codec 芯片 i2s 引脚与 RK3399 i2s1连接。软件上需要加下述patch(以 rt5640 为例):
DTS配置 / { rt5640-sound { status = "okay"; compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,name = "rockchip,rt5640-codec"; simple-audio-card,mclk-fs = <256>; simple-audio-card,widgets = "Microphone", "Mic Jack", "Headphone", "Headphone Jack"; simple-audio-card,routing = "Mic Jack", "MICBIAS1", "IN1P", "Mic Jack", "Headphone Jack", "HPOL", "Headphone Jack", "HPOR"; simple-audio-card,cpu { sound-dai = <&i2s1>; }; simple-audio-card,codec { sound-dai = <&rt5640>; }; }; }; &i2s1 { status = "okay"; #sound-dai-cells = <0>; rockchip,i2s-broken-burst-len; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; assigned-clocks = <&cru SCLK_I2S_8CH>; assigned-clock-parents =<&cru SCLK_I2S1_8CH>; }; &i2c1 { status = "okay"; rt5640: rt5640@1c { #sound-dai-cells = <0>; compatible = "realtek,rt5640"; reg = <0x1c>; clocks = <&cru SCLK_I2S_8CH_OUT>; clock-names = "mclk"; realtek,in1-differential; realtek,in2-differential; pinctrl-names = "default"; pinctrl-0 = <&i2s_8ch_mclk>; status = "okay"; }; }; 时钟配置 diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index f434454..f5822f0 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -712,7 +712,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, RK3399_CLKGATE_CON(8), 11, GFLAGS), - MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, + MUX(SCLK_I2S_8CH, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(30), 8, 2, MFLAGS, diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index d32ce01..710d610 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -226,6 +226,7 @@ #define ACLK_GIC_PRE 262 #define ACLK_VOP0_PRE 263 #define ACLK_VOP1_PRE 264 +#define SCLK_I2S_8CH 265 /* pclk gates */ #define PCLK_PERIHP 320 |
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