完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
编辑:我用上一个帖子中的信息修复了我的上一个错误,这不幸的是没有完全解决我的问题。
我在:xilinx webpack ISE,斯巴达3E basys 2板,50Mhz时钟。 这个论坛出于某种奇怪的原因,也不会让我更新我的最后一个帖子。所以基本上我只想创建一个允许LED保持10秒钟然后关闭10秒钟的计时器。 是我的代码: - 模块SenseCircuit( //输入 输入时钟, //输出 输出Testlight1 //测试灯每隔10秒在开启和关闭之间切换 ); reg [28:0]柜台; //在50MHz时钟10秒后计数重置 reg Testlight1var; 最初开始 Testlight1var = 0; //当我打开FPGA时,将两个变量归零 counter = 0; 结束 总是@(posedge clock) 开始 counter = counter + 1; if(counter == 500_000_000)///如果计数器达到10秒,则启动下面的代码 开始 counter = 0; Testlight1var = ^ Testlight1var; // xor testlightvar的当前值 结束其他开始 //如果没有达到10秒,则什么也不做 结束 结束 分配Testlight1 = Testlight1var; //将testlight输出分配给测试灯变量 endmodule 我的ucf只是: - NET“时钟”LOC =“B8”; NET“Testlight1”LOC =“N4”; 它不起作用,我收到很多警告,如下所示: - (当选择合成时) 警告:Xst:653 - 使用信号但从未分配信号。 此无源信号将自动连接到值0.WARNING:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(1).prj丢失。 警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(2).prj丢失。 警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(3).prj丢失。 警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(5).prj丢失。 警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(6).prj丢失。 当我选择:恭维设计 警告:PhysDesignRules:367 - 信号不完整。 信号 不会在设计中驱动任何负载引脚。 警告:参数:288 - 信号clock_IBUF无负载。 PAR不会尝试路由此信号。 警告:参数:283 - 此设计中有1个无负载信号。 此设计将导致Bitgen发出DRC警告。 警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(1).prj缺失。警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(2).prj丢失。警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(3).prj丢失。警告:ProjectMgmt - 文件C: / Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(5).prj缺失。警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(6) .prj不见了。 最后当我选择:生成编程文件我得到: - 警告:PhysDesignRules:367 - 信号不完整。 信号 不会驱动设计中的任何负载引脚。警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(1).prj缺失。警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(2).prj缺失。警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(3).prj 缺少。警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project Lab 1 FPGA / Sensecircuit / SenseCircuit(5).prj缺失。警告:ProjectMgmt - 文件C:/ Users / Amuka / Google Drive / Project 实验1 FPGA / Sensecircuit / SenseCircuit(6).prj丢失。 这些警告可能是什么原因? 这是说Testlight1var尚未使用我正在使用它和Xor'ng它为我的LED。当我将代码上传到fpga板时,没有任何反应; 我看到没有闪烁的LED。我怀疑它可能是我的XOR政治家,但就我而言,它是一个合法的运营商。你的同意将非常感激。 以上来自于谷歌翻译 以下为原文 EDIT:I fixed my last errors with information from my last thread, this unfourtunately did not completely solve my problem. I am on :xilinx webpack ISE, spartan 3E basys 2 board, 50Mhz clock. It is also unfourtunate that the the forum for some weird reason, is not letting me update my last thread.so anyway basically I just want to create a timer that allows a LED to stay on for 10 seconds , then off for 10 seconds.This is my code:- module SenseCircuit( //Inputs input clock, //Outputs output Testlight1 //test light that will alternate between on and off every 10 seconds );reg [28:0] counter; //counts up resets after 10 seconds of a 50MHz clock reg Testlight1var;initial begin Testlight1var=0; //zero out both variables when I turn on the fpga counter =0;endalways @(posedge clock) begincounter =counter+1;if(counter==500_000_000) ///if counter reaches 10 seconds start the code belowbegincounter =0;Testlight1var=^Testlight1var; //xor the current value of testlightvarend else begin //do nothing if 10 seconds not reached end endassign Testlight1 =Testlight1var; //assign testlight output to test light variable endmodulemy ucf is just :- NET "clock" LOC = "B8";NET "Testlight1" LOC = "N4"; It's not working and I am getting alot of warnings which such as below:- (when select synthesize) WARNING:Xst:653 - Signal WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (1).prj is missing.WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (2).prj is missing.WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (3).prj is missing.WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (5).prj is missing.WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (6).prj is missing.when i select :impliment design WARNING:PhysDesignRules:367 - The signal WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (2).prj is missing. WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (3).prj is missing. WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (5).prj is missing. WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (6).prj is missing. Finally when i select :generate programming file I get :- WARNING:PhysDesignRules:367 - The signal WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (2).prj is missing. WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (3).prj is missing. WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (5).prj is missing. WARNING:ProjectMgmt - File C:/Users/Amuka/Google Drive/Project Lab 1 FPGA/Sensecircuit/SenseCircuit (6).prj is missing. what could be the cause of these warnings?? It is saying Testlight1var is not used yet I i am using it and Xor'ng it for my LED. when i upload the code to the fpga board , nothing happens; I see no blinking LED.I suspect it could be my XOR statemen, but as far as I am concerned it is a legitemate operator.Your assitance would be much appreciated on this. |
|
相关推荐
4个回答
|
|
编辑,因为我无法编辑该帖子:我的错误,你实际上将Testlight1var设置为等于其自身的XOR。
我不确定如何定义单输入XOR。 然而,实际上,用我之前建议的任何一个(即将Testlight1var设置为NOT本身,或者将其与1进行异或)替换它应该有效。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 An edit, because I can't edit that post: my mistake, you're actually setting Testlight1var equal to the XOR of itself. I'm not sure how a single-input XOR is defined. In practical terms, however, replacing it with either of the ones I suggested earlier (ie setting Testlight1var equal to NOT itself, or XORing it with 1) should work. View solution in original post |
|
|
|
我认为你有更新Testlight1var的错误逻辑。
与自身异或的任何值都将为零。 因此,Vivado刚刚将Testlight1var与零绑定。 实现目标的更常见方式是: Testlight1var = ~Testlight1var; 或者,等效地: Testlight1var ^ = 1'b1; 以上来自于谷歌翻译 以下为原文 I think you've got the wrong logic for updating Testlight1var. Any value XORed with itself is going to be zero. Therefore Vivado has just tied Testlight1var to zero. The more common way to achieve your goal would be: Testlight1var = ~Testlight1var;Or, equivalently: Testlight1var ^= 1'b1; |
|
|
|
编辑,因为我无法编辑该帖子:我的错误,你实际上将Testlight1var设置为等于其自身的XOR。
我不确定如何定义单输入XOR。 然而,实际上,用我之前建议的任何一个(即将Testlight1var设置为NOT本身,或者将其与1进行异或)替换它应该有效。 以上来自于谷歌翻译 以下为原文 An edit, because I can't edit that post: my mistake, you're actually setting Testlight1var equal to the XOR of itself. I'm not sure how a single-input XOR is defined. In practical terms, however, replacing it with either of the ones I suggested earlier (ie setting Testlight1var equal to NOT itself, or XORing it with 1) should work. |
|
|
|
谢谢你做了这个伎俩,我也非常,非常感谢这个解释。我最终使用了否定运算符(〜)。特别感谢toavrumw帮助我的最后一个帖子,再次感谢快速响应的人!
以上来自于谷歌翻译 以下为原文 Thanks that did the trick, I also very, very much appreciate the explanation.I ended up using the negation operator(~).Special thanks to avrumw for helping out in my last thread, thanks again for the fast responses guys!! |
|
|
|
只有小组成员才能发言,加入小组>>
2388 浏览 7 评论
2804 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2270 浏览 9 评论
3338 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2440 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
768浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
551浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
386浏览 1评论
1975浏览 0评论
692浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-11-29 09:16 , Processed in 1.361241 second(s), Total 85, Slave 68 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号