请问DMA的行为和依赖性该怎么解释？

你好，
我想配置1个DMA通道从P-端口到USB与几个缓冲区。
（a）是的，这是可以做到的。
P-端口套接字有可能将数据写入一个缓冲器，而USB套接字同时读取另一个缓冲器吗？
要配置这个DMA通道需要多少缓冲区？
（a）是的，这是可能的。为此需要至少有两个缓冲区。一个将被P-端口占用，另一个将被USB块占用。
一个缓冲区的大小取决于USB端点配置吗？
缓冲区的数量取决于USB端点配置吗？
（a）通常声明的是端点最大分组大小的倍数的缓冲器大小通常是好的实践。DMA通道中的缓冲区数量与端点配置没有真正的关系。但是，在端点配置中配置的突发大小与缓冲区一样多，这是一个很好的做法。
DMA准备标志如何依赖于DMA缓冲区状态？
它只描述一个缓冲状态或所有缓冲状态吗？
“活动”状态指示缓冲器准备就绪吗？
DMA水印标志如何依赖于DMA缓冲器状态？
（a）对于向P端口输出数据的信道（到外部芯片/设备），DMA就绪标志指示是否有数据准备从任何缓冲器读出。如果至少有一个缓冲器有数据提交到P端口，则DMA就绪标志被取消声明。在这种情况下，它本质上是一个空标志。
对于向P端口（从外部芯片/设备）输入数据的信道，DMA就绪标志指示是否存在可写入的缓冲区。如果存在至少一个可用数据填充的缓冲器，则DMA就绪标志被去断言。在这种情况下，它基本上是一个完整的标志。
此标志的极性可以在GPIFII设计器中设置。
DMA就绪标志操作取决于通道中有多少缓冲器可用，DMA水印告诉您缓冲区中有多少字节可用。您可以使用API在固件中设置水印级别。
水印一般用于使外部处理器接口的FX3的GPIF获取缓冲区满事件提前通知。在所有的旗帜有FX3至少2周期延迟实际的事件和通知传播到GPIF接口。因此水印标志有助于克服这个限制。
当做
沙肖克



     以下为原文
   Hi,
     
    [size=10.909090995788574px] I want to configure 1 DMA channel from P-Port to USB with several buffers.
    [size=10.909090995788574px](A) Yes, this can be done.
    [size=10.909090995788574px] 
    [size=10.909090995788574px]    Is it possible that P-Port socket writes data to one buffer and USB socket reads from another buffer simultaniously?
    [size=10.909090995788574px]   What minimal number of buffers do I need to configure for this DMA channel  to do this?
    [size=10.909090995788574px](A) Yes, this is possible. You need to have a minimum of two buffers for this. One will be engaged by the P-port and the other will be engaged by the USB block.
    [size=10.909090995788574px] 
    [size=10.909090995788574px]   How does size of one buffer depend on USB endpoint configuration?
    [size=10.909090995788574px]   How does number of buffers depend on USB endpoint configuration?
    [size=10.909090995788574px](A) It is generally good practice to declare buffer sizes which are a multiple of endpoint max packet size. Number of buffers in the DMA channel does not really have a relation to endpoint config. But it is good practice to have as many buffers as the burst size configured in endpoint config.
    [size=10.909090995788574px] 
    [size=10.909090995788574px]   How does DMA ready flag depend on DMA buffers state?
    [size=10.909090995788574px]   Does it describe only one buffer state or all buffers state?
    [size=10.909090995788574px]   Does 'active' state indicate buffer readiness to write?
    [size=10.909090995788574px]   How does DMA watermark flag depend on DMA buffers state ?
    [size=10.909090995788574px](A) For a channel that outputs data to the P-port (to external chip/device), the DMA ready flag indicates whether or not there is data ready to be read out from any of the buffers. If there is at least one buffer with data committed to the P-port, DMA ready flag is deasserted. It is essentially a empty flag in this case.
    [size=10.909090995788574px]For a channel that inputs data to the P-port (from external chip/device), the DMA ready flag indicates whether or not there is buffer area available to write into. If there is at least one buffer available to be filled with data, the DMA ready flag is deasserted. It is essentially a full flag in this case.
    [size=10.909090995788574px]The polarity of this flag can be set in GPIFII Designer.
    [size=10.909090995788574px]While the DMA ready flag operation depends on how many buffers in the channel are available, the DMA watermark tells you how many bytes in a buffer are available. You can set the watermark level in firmware using a API.
    [size=10.909090995788574px]The watermark is generally used so that the external processor interfaced to FX3's GPIF gets an early notification of the buffer full event. All flags within FX3 have a min. 2 cycle delay between the actual event and its notification propagating to the GPIF interface. So the watermark flag helps overcome this limitation.
    [size=10.909090995788574px] 
    [size=10.909090995788574px] 
    [size=10.909090995788574px]Regards
    [size=10.909090995788574px]Shashank

海洛
非常感谢你这么详细的回答。
这对我很有用。
国王的问候，
奥尔加。



     以下为原文
  Helllo,
    Thank you very much for so detailed answer.
    It was very usefull for me.
    King Regards,
    Olga.

你的回答有点混乱。
对于向P端口（从外部芯片/设备）输入数据的信道，DMA就绪标志指示是否存在可写入的缓冲区。如果存在至少一个可用数据填充的缓冲器，则DMA就绪标志被去断言。在这种情况下，它基本上是一个完整的标志。
你在用“DeSufft”这个词对我来说意味着信号处于虚假状态。即DeSault意味着DMA准备不是真的。如果信号是活动的高电平，那么DeSufft将意味着它处于逻辑低电平。
这就是你想要描述的方式吗？你说如果至少有一个缓冲器准备好了，DMA准备好了吗？如果GPIF接口能够接收数据到缓冲器，那么DMA准备就绪（即变得活跃，意味着高电平信号的逻辑高）。
请你澄清一下好吗？
DMA就绪标志操作取决于通道中有多少缓冲器可用，DMA水印告诉您缓冲区中有多少字节可用。您可以使用API在固件中设置水印级别。
AN6997的第17页指出，不能使用部分标志来表示套接字的可用性，但它不能解释为什么会出现这种情况。如果我有4KB DMABUFFER并设置部分标志来声明（变得活跃），当缓冲区中的缓冲区小于4096个字节时，我不能使用这个标志来指示有一个完全空的缓冲区可用吗？



     以下为原文
   Your answer is a little confusing.
    [size=10.909090995788574px]For a channel that inputs data to the P-port (from external chip/device), the DMA ready flag indicates whether or not there is buffer area available to write into. If there is at least one buffer available to be filled with data, the DMA ready flag is deasserted. It is essentially a full flag in this case.
    You are using the word "deassert" which to me means the signal is in its false state. i.e. deassert means DMA Ready is not true. If the signal is active-high, then deassert would mean that it is at a logic low level.
    Is this how you are intending the description? You say that if there is at least one buffer ready the DMA Ready de-asserts? I would have expected that if the GPIF interface is able to receive data into a buffer then DMA Ready would be asserted (i.e. become active, meaning logic high for active-high signals).
    Can you please clarify?
    [size=10.909090995788574px]While the DMA ready flag operation depends on how many buffers in the channel are available, the DMA watermark tells you how many bytes in a buffer are available. You can set the watermark level in firmware using a API.
    [size=10.909090995788574px] 
    [size=10.909090995788574px][size=10.909090995788574px]Page 17 of AN65974 states that a partial flag cannot be used to signal the availability of a socket, but it does not explain why this is the case.  If I have 4kB DMA buffers and [size=10.909090995788574px]set the partial flag to assert (become active) when the buffer has less than 4096 bytes in it[size=10.909090995788574px] can I not use this flag to indicate that there is a completely empty buffer available?

我想分享我从赛普里斯清除了速度信息。1为他们的支持案例工作者，谢谢！
首先，“dma_rdy”实际上是一个信号，就是说当没有满足要求的DMA缓冲区（读或写）--这是非常迷惑，因为“DMA准备”，我和任何人我问听起来像是一个信号，声称当DMA操作应继续进行。总之…如果你认为信号为“DMA不可用”然后事情开始变得很有意义。给我的例子有助于理解：
假设你有一个带有4个1KBDMA缓冲器的DMA描述符。让我们说你要转移到GPIF把数据传输到FX3（即DMA操作）。当系统首先初始化，所有4缓冲区是空的。因为至少有一个缓冲区可用，dma_rdy不会断言。FPGA传输1KB的数据。现在有1个缓冲区满，3个缓冲区是空的。DMAYRDY将继续处于非活动状态。FPGA转让另一个1KB…现在你有2个满，2个空，DMAYRDY保持不活动。传输另一个1KB。3满，1空，DMAYRDY仍然无效。换乘1KB。现在你有4个满满的，0个空的。DMAYRDY现在断言。记住，DMAYRDY真的意味着“DMA没有准备好”。
的dma_rdy国旗仍然断言，现在到那种完全清空缓冲区（例如，它是由USB周边消耗）。现在你有三，一空，因为至少有一个DMA缓冲区可用的转移，dma_rdy会断定，信令FPGA现在可以传输数据了。
我特意用词断言/主动去断言/无效因为国旗可以配置为高电平或低。而补救，我会包括这个完整性：高一个积极的信号，肯定意味着输出将处于逻辑高，并断定装置的输出将在逻辑低。对于有源低信号，正好相反。即为低电平，当信号有效时，该引脚为逻辑低，当它是去断言，该引脚为逻辑高。
就我个人而言，我对这个标志的两个方面感到困惑：
dma_rdy意味着“DMA没有准备好”或“DMA”，它声称当DMA传输不能进行dma_rdy旗报道为DMA描述符中的任何线程缓冲区的可用性，而不是当前的缓冲区。这在事后看来有很大的意义。关于DMAX部分标志：
DMA部分国旗不能用于启动DMA传输因为这个标志的状态不确定时的描述符被更新使用下一个缓冲区。这在文档中没有描述。这就是为什么dma_rdy必须开始转移，和dma_partial可以用来结束一个转移如果简单的统计数据是不够的。
这将是如果文件被更新，阐述这些观点极大的赞赏。这个标志的命名真的很糟糕。



     以下为原文
   I wanted to share the information I got from Cypress which clears things up considerably. +1 for their support case workers, thank you!
    First, "DMA_RDY" is actually a signal that is asserted when there is no DMA buffer available to satisfy the request (read or write) -- this is very confusing because "DMA Ready" to myself and anyone I've asked sounds like a signal that is asserted when the DMA operation should proceed.  Anyway... If you think of the signal as "DMA NOT AVAILABLE" then things start to make a lot of sense. The example given to me helps this understanding:
    Let's say you have a DMA descriptor with 4 1kB DMA buffers. Let's also say you want the transfer to take data from GPIF and transfer it into the FX3 (i.e. a DMA IN operation). When the system is first initialized, all four buffers are empty. Since there is at least one buffer available, DMA_RDY will NOT be asserted.  The FPGA transfers 1kB of data. Now you have 1 buffer full, 3 buffers empty. DMA_RDY will remain in its inactive state. The FPGA transfers another 1kB... now you have 2 full, 2 empty, and DMA_RDY stays inactive. Transfer another 1kB. 3 full, 1 empty, DMA_RDY still inactive.  Transfer 1kB. Now you have 4 full, 0 empty. DMA_RDY now asserts. Remember that DMA_RDY really means "DMA not ready".
    The DMA_RDY flag will remain asserted now until one of those buffers is completely emptied (e.g. it was consumed by the USB peripheral). Now you have 3 full, 1 empty and since there is at least one DMA buffer available to transfer, DMA_RDY will de-assert, signalling the FPGA that it can now transfer data again.
    I have specifically used the words assert/active and de-assert/inactive beause the flag can be configured as active-high or active-low. While remedial, I will include this for completeness: for an active-high signal, assert means that the output will be at a logic high, and de-assert means the output will be at a logic low.  For an active-low signal, the opposite is true. i.e. for active-low, when the signal is asserted, the pin is at a logic low, and when it is de-asserted, the pin is at a logic high.
    Personally, I was confused by two aspects of this flag:
   

    

• DMA_RDY means "DMA not ready" or "DMA full" -- it asserts when a DMA transfer cannot be performed    
  
• The DMA_RDY flag reports the availability of ANY buffer in the descriptor for the DMA thread, not the current buffer. This makes a lot of sense in hindsight.   
  

    Regarding the DMA_PARTIAL flag:
    The DMA PARTIAL flag cannot be used to start a DMA transfer because the state of this flag is indeterminate during the time when the descriptor is being updated to use the next buffer. This is not described in the documentation. This is why DMA_RDY must be used to start a transfer, and DMA_PARTIAL can be used to end a transfer if simple data counting is insufficient.
    It would be greatly appreciated if the documentation were updated to elaborate on these points. The naming of this flag is really, really bad.

谢谢你的信息！
-文档团队10。需要一个示例项目
为什么我们不能从柏树员工那里直接得到这些信息呢？



     以下为原文
  Thanks for the info!
     
    -10 for the documentation team though.  An example project is required IMHO
     
    And why are we not getting this direct from Cypress employees?

希科尔史密斯
我不能理解“DMAXX部分可以用来结束传输，如果简单的数据计数是不够的”，你能详细解释一下吗？
谢谢！



     以下为原文
  Hi akohlsmith
     I can not understand "DMA_PARTIAL can be used to end a transfer if simple data counting is insufficient", can you explain it in detail?
    Thanks!

你好，
因此，有一些特殊的步骤来确保这些DMA缓冲区不相互作用/重叠。只需设置DMACONFIGO大小就安全吗？例如，为UB3.0的数据通道设置一个16K，然后为另一个DMA通道设置另一个16字节。他们会很好吗？



     以下为原文
  Hi,
    So is there some special steps to take to make sure that these DMA buffer does not interact/overlap with each other. Will it be safe just by setting the dmaConfig.size respectively? For example, setting the one for the channel of USB3.0 data transfer to 16K and then setting another one 16 byte for other DMA channels. Will they just work fine?

我在DMA遇到麻烦了，上面的评论可能对我有用。
我应该花些时间了解这些信息。



     以下为原文
  I failed in trouble with DMA now, the above comments maybe are useful for me. 
    I should take some time to understand these information.