请问IDAC +电流镜会比VDAC +电流转换器更好吗？

我以前用过这个方法，在A中增加了动态范围。
LV情况，3.3V操作，并且非常有效地去除
镜面输入端的兼容问题。以你为例
同时在电流镜输出端获得高压电压。这个
明显的挑战是晶体管匹配，线性等。
镜子容易下沉，源点难度的影响
VDD，或镜面方程的高侧参考效应。
有很多信息网站，只是睁眼”电流镜的设计”，你
将阅读到下个世纪。
问候，Dana。



     以下为原文
  I used that method in the past do get increased dynamic range in a
    LV situation, 3.3V operation, and was very effective at removing the
    complience issues on the input side of the mirror. In your case you
    also get the HV ability on the output side of the current mirror. The
    obvious challenges are transistor matching, linearity, etc.....
     
    Sink mirrors easiest, source a little more challenging because of the effects
    of Vdd, or high side reference effects on mirror equations.
     
    There is a lot of info on web, just goggle "current mirror design", you
    will be reading well into the next century.
     
    Regards, Dana.

就拓扑而言，最简单的一个看起来是——
你应该做一个错误分析，看看你的目标是否得到满足。
问候，Dana。



     以下为原文
  As far as topology, one of the simplest looks like -
     
     
    You should do an error analysis to see if your goals are met.
     
    Regards, Dana.

一个很好的参考镜子
HTTP://HyrEd.McGRAW-HIL.COM/SITES/DL/FRIE/070601624/37358/JAE20990YCH16.PDF
问候，Dana。



     以下为原文
  A good reference on mirrors -
     
    http://highered.mcgraw-hill.com/sites/dl/free/0070601623/337358/jae20990_ch16.pdf
     
    Regards, Dana.

谢谢你提供的信息。我知道转发器匹配问题，但我现在发现一个集成的电流镜像IC。不知道这会不会有帮助。
您张贴的图像类似于我的电压控制电流源（见PIC）。然而，我似乎不能选择正确的晶体管。当负载超过某一点时，所有的模拟都失败了，但是在电压符合范围内。
此外，我正在考虑使用开关方案或电流转向方案来改变电流方向与负载。这将允许我使用一个拓扑。
你喜欢VDAC +电压控制电流源的IDAC +电流镜解决方案？
维康
13.7 K



     以下为原文
   Thanks for the info. I'm aware of transitor matching issues, but I am currently find an integrated current mirror IC. Don't know if that will help.
    The images you posted are similar to my voltage controled current source (see pic). However I can't seem to choose the correct transistor. All my simulations are failing when my load gets above above a certain point, but within voltage compliance.
    Also, I'm considering usinga switching scheme or current steering scheme to change current  direction withing the load. That will allow me to use one topology. 
    Would you prefer the VDAC + voltage controled current source over the iDAC + current mirror solution?

•   Vcon_Isource.png 13.7 K
  
  

我倾向于用Wilson电流镜来使用IDAC。
HTTP://E.WiKiTo.Org/Wiki/Wixon Curruty-反射镜
问候，Dana。



     以下为原文
   My inclination would be to use IDAC with a Wilson current mirror.
      
     
      
     http://en.wikipedia.org/wiki/Wilson_current_mirror
      
     Regards, Dana.

您将选择哪些组件来实现该解决方案？我想用IDAC以最少的仪式刺激大脑切片，但我不知道什么是可用的…干杯



     以下为原文
   What components would you choose to implement that  solution? I'd like to use IDAC with a minimum of ceremony to stimulate brain slices but I don't know what's available... Cheers

在Wilson电流镜中显示Q1和Q2是希望的。
相配的。关于半和Fairchild匹配晶体管对
这很容易。几乎所有的Vcesus & 20 V。
问候，Dana。



     以下为原文
  In the wilson current mirror shown Q1 and Q2 would like to be
    matched. ON Semi and Fairchild have matched transistor pairs
    that make this easy. Pretty much all with Vcesus > 20 V.
     
    Regards, Dana.

好啊。我回到了当前镜像问题。我用DANA发布的OpAMP解决方案取得了一些成功。我想消除对任何运算放大器的需求，并使用IWAC作为参考电流的Wilson或共源共栅电流镜。我的应用程序要求我使用一个被引用到GND的A+和-12V，如所附图像中所见。只有当我使用3.3V作为公共电压而不是12V时，我才能得到具有P MOSFET的电流接收器设计。
问题：我如何用内部IDAC来实现12V源和汇电流镜（参见图像）？
FIY：这里有一些有用的IDAC信息：HTTP://CyPress？COM/？DOCID＝42985
IDAC-CurrNeTyMur.PNG
50.2 K



     以下为原文
  Ok. I'm back the the current mirror problems. :) I've has some success using the opamp solutions that dana posted. I would like eliminate the need for any opamp and use a wilson or cascoded current mirror with an IDAC as the reference current. My application requrires that I use a + and -12V referenced to gnd as seen in the attached images. I can only get the current sink design with P-mosfets to work only if I use 3.3V as the common voltage and not 12V. 
 
    Question: How can I impliment a 12V source and sink current mirror using the internal IDAC (see image) ?
    FYI: Here's a good artical with some useful IDAC info: http://www.cypress.com/?docID=42985

•   idac-current_mirror.png 50.2 K
  
  

不确定图像是否正确导入。又来了。



     以下为原文
    Not sure that the image imported correctly. Here it is again.

最后尝试与图像。请阅读以上文章，以帮助我回答我的问题。



     以下为原文
   Last try with the image. Please read above post to help me answer my question. 
     
   

一些问题
1）你需要设计多少顺应性？我问的理由
PMOSFETs的高阈值会占用该裕量。加上它们的有效性
GM & LT＆LT；双极性，读取电流调节的影响。
2）负载必须接地，它能补偿CM电压吗？
3）这是直流设计吗？如果不是，你需要什么样的AC性能？
问候，Dana。



     以下为原文
  Some questions -
     
    1) How much complience do you need to design to ? Reason I ask
    is PMOSFETs high threshold will eat into that margin. Plus their effective
    Gm << Bipolar, read impact on current regulation.
     
    2) Does load have to be grounded, can it accomidate CM voltage, eg float ?
     
    3) Is this a DC design ? If not what is the AC performance you need out of the Isource ?
     
    Regards, Dana.

用电流镜，电压会被施加到DAC输出管脚上？



     以下为原文
   With the current mirror, what would be the voltage applied to the DAC output pin?

在双极性Wilson阱为2×VBE的情况下，源镜2＊VBE
低于VDD轨的源镜。
在MOSFET威尔逊的情况下，它是2×VTH任一轨道，排水饱和模式。
问候，Dana。



     以下为原文
  In the case of bipolar Wilson sink that is 2 * Vbe above ground, source mirror 2 * Vbe
    below Vdd rail of the source mirror.
     
    In case of MOSFET Wilson it is ~ 2 * Vth off either rail, drains in saturatiion mode.
     
    Regards, Dana.

Dana：
1。我希望在-100uA到100uA的负载上有+-10V的顺应性。MOSFET的我看着使用先进设备对线性匹配。P和N均为0.7V VTH。它们提供的是0V VN。
2。负载必须接地。负载生物组织和我会同时记录。我可能对地面中的电源，但我不想改变我目前的记录设计太多。更容易添加-12V电源。
三。这不是一个直流设计。我提供“广场”的脉冲电流幅值高达- 100ua或100ua与0.5-1ms时间。波的不太关键的上升和下降时间，但<；50us最好。
HL：在该引脚电压会12v-2 * 0.7v = 10.6v。这是太多的PSoC引脚。因此，这是我在寻找一个替代方案的原因。
我附上一个另类的设计，我一直玩模拟。也使用ALD匹配对MOSFET。
ALD105双极电流镜
22.9 K



     以下为原文
  Dana:
     
    1. I'd like to have +-10V compliance on the load with -100uA to 100uA. The MOSFET's i'm looking at using are matched pairs from Advanced Linear Devices. Both the P and N have 0.7V Vth. They offer N's with 0V Vth. 
     
    2. The load must be grounded. The load is biological tissue and I will be simultaneously recording from. I could bias the ground to mid supply, but I didn't want to alter my current recording design too much. It's easier to add a -12V supply.
     
    3. This is not a DC design. I'm delivering "square" pulses of current with amplitudes up to -100uA or 100uA with 0.5-1ms duration. The rise and fall time of the wave aren't too critical, but < 50us would be best.
     
     
    HL: The voltage at the pins would be 12V-2*0.7V=10.6V. Which is too much for the PSoC pins. Thus, this is the reason I'm looking for an alternative solution.
     
    I'm attaching an alternative design that I've been playing around with in simulations. Also using ALD matched pair MOSFETS.

•   ALD1105 Bipolar Current Mirror.png 22.9 K
  
  

谢谢Jram，这正是我想知道的。



     以下为原文
   thanks Jram, that's what I was wondering. 

ALD部分很有趣，我没有意识到它们。
看来，总体精度将在很大程度上由镜子中的GM错误控制。我愿意
要想知道你的调味品是如何做到这一点的。然而，PSoC IDAC
有5%的错误。但PSOC的参考文献很好。1%。您可以运行CAL例程。
Delsig以减轻或使用VREF派生的I源/接收器，而不是IDAC。决策支配
通过做一个端到端的错误分析，看看它是否符合你的目标。
我想你会用IOAD测量有兴奋组织的Vult。如果你正在使用
PSOC当然会违反CM范围的引脚/ A/D，例如在负载时所需的顺应性。
看起来像隔离差放大器的可能性，也摆脱了地面CM。模拟设备
浮现在脑海中。
非常有趣的设计。
问候，Dana。



     以下为原文
  The ALD parts pretty interesting, I was not aware of them.
     
    Looks like overall accuracy will be largely governed by gm mismatc in the mirrors. I would
    be curious to know how your spice sims work out regarding this. However the PSOC IDAC
    has a 5% error.  But PSOC reference is good to .1%. You could either run a cal routine with
    DelSig to alleviate this or use a Vref derived I source/sink, instead of IDAC. Decision governed
    by doing an end to end error analysis to see if it meets your goals.
     
    I assume you will be measuring the Vload having excited tissue with Iload. If you are using
    PSOC that of course will violate CM range for pins / A/D, eg. complience needed at load.
    Looks like isolated diff amp possibility, gets rid of ground CM as well. Analog Devices
    comes to mind.
     
    Very interesting design.
     
    Regards, Dana.