请问有什么办法来确保所有的位都被完全传输？

在写一个字节到SPI之后，什么是推荐的方法来确保所有的位都被完全传输？我的应用程序只写（从不读取）。它还需要等待每个字节被完全发送，因为在每个字节之后，一个单独的硬件脉冲必须发送到接收器，这使得接收器处理接收到的字节。最初，我的写入和轮询看起来是这样的：但是上面的代码看起来是不可靠的。我认为这个问题是一个竞赛：在字节到达移位寄存器之前（即字节仍在FIFO中工作），可以很快轮询移位寄存器，在这种情况下，在字节被发送之前轮询结束。这种失败将是时间相关的，对ISRs正在运行的内容非常敏感。根据我的阅读，我得到的印象是，我应该轮询SPixType，如下：SPI文档只说SPICONTHOST＝1意味着“SPI外围设备目前正忙于一些事务。”忙位保持设置，直到所有挂起的事务完成，经验表明这是真的。但是SPI文档没有说明什么时候比特被设置。在硬件有机会设置它响应缓冲区写入之前，是否可以很快轮询SPILASH？或者SpBiF的写入保证了SPICONT的设置？换句话说，SPI模块是否向SPIBUF写入并设置SPIBUSY atomic？请注意，我已经启用了FIFO，因为这是和谐设置它，但它没有获得任何东西，因为需要在每个字节之后等待。我使用的是PIC32 MZ1024ECG144。



      以下为原文

    After writing a byte to SPI, what's the recommended method of polling to ensure that all its bits have been entirely transmitted?

My application does writes only (never reads). It also needs to wait for each byte to be completely sent, because after each byte a separate hardware pulse must be sent to the receiver, which causes the receiver to process the received byte.

Originally my write and polling looked like this:

PLIB_SPI_BufferWrite(SPI_ID_1, data);
while (!PLIB_SPI_TransmitBufferIsEmpty(SPI_ID_1));
while (!PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_ID_1));
// assume SPI transaction complete

But the above code appears to be unreliable. I assume the issue is a race: it's possible to poll the shift register too soon, before the byte reaches the shift register (i.e. the byte is still working its way through the FIFO), in which case polling ends before the byte has been sent. This failure would be timing-dependent and sensitive to what ISRs were running etc.

Based on my reading I get the impression that I should poll SPIBUSY instead, as follows:

PLIB_SPI_BufferWrite(SPI_ID_1, data);
while (PLIB_SPI_IsBusy(SPI_ID_1));
// assume SPI transaction complete

The SPI doc says only that SPIBUSY = 1 means "SPI peripheral is currently busy with some transactions." I take this to mean that the busy bit remains set until all pending transactions are completed, and experience suggests this is true. But the SPI doc says nothing about when the bit becomes set. Is it possible to poll SPIBUSY too soon, before the hardware has had a chance to set it in response to the buffer write? Or does writing to SPIBUF guarantee that SPIBUSY is set? In other words, does the SPI module make writing to SPIBUF and setting SPIBUSY atomic?

Note that I have the FIFO enabled, because that's how HARMony set it up, but it doesn't gain me anything, due to the need to wait after each byte. I'm using the PIC32MZ1024ECG144.