在SPI增强模式下接收如何确定何时将所有字节移入SPIxRXB？

我使用SPI增强模式，8位数据宽度。当尝试确定何时接收到所有接收到的FIFO字节时，我遇到了意想不到的行为。步骤如下……初始化SPI模块如下…具体地，对于这个讨论，注意StxISel& lt；SpxCon＝＝‘00’（SPIXTXIF是当最后一个转移从SPISR移出并且发送操作完成时被设置）调用SPIXXFER（PYDST，LEN），其中PyDST是RAM地址到WRI。TE to，和LeN是读取到FIFO SPIXTXBBY的字节数，将每个字节连续写入SPIxBUF（LeN & lt；16）的透明SPIxTXIFwait，以使所有的SPIXTXBB字节移动到PixSRand并移出，并且所有字节移位ItoSpxSrand并移动ItOnPixRxB。由于接收到的数据可能小于16字节，所以我认为我可以使用SPIXTXIF断言，这意味着所有的传输字节都被移出SPIxSR，并且（我假设）所有接收字节移位到SPIXSR并移动ItOxPixRxb）。显然我在第5步错了！目前，SPIXTXIF断言，并不是所有的字节都接收到了ItOxPixRxB！相反，唯一能发现所有预期字节的方法是重复PulfXxStas.RxBuffelm，直到该值与发送的字节数相匹配。有更好的方法可以使用中断吗？（我正在考虑如何在这个过程中使用DMA）。



      以下为原文

    I am using SPI Enhanced mode with 8-bit data width.  I have encountered an unexpected behavior when attempting to determine when all bytes are received into the receive FIFO.  Steps are as follows...

• Initialize SPI module as follows...
     SPI2CON =   (0b00<<0 ) // SRXISEL<1:0>, SPIxRXIF set when last byte is read (buffer is empty)
               + (0b00<<2 ) // STXISEL<1:0>, SPIxTXIF set when last byte is shifted out of SPISR and TX operations are complete
               + ( 0b0<<4 ) // DISSDI, SDIx pin is controlled by the SPI module
               + ( 0b1<<5 ) // MSTEN, Master mode
               + ( 0b0<<6 ) // CKP, Clock idle state is low; active state is high
               + ( 0b0<<7 ) // SSEN, SSx pin not used for Slave mode (controlled by port)
               + ( 0b1<<8 ) // CKE, Slave Output data changes on clock active-to-idle transition
               + ( 0b0<<9 ) // SMP, Input data sampled at middle of data output time
               + (0b00<<10) // MODE<32,16>, 8-bit mode
               + ( 0b0<<12) // DISSDO, SDOx pin is controlled by the module
               + ( 0b0<<13) // SIDL, Continue operation in Idle mode
               + ( 0b1<<15) // ON, enable SPI2
               + ( 0b1<<16) // ENHBUF, Enhanced Buffer mode is enabled
               + ( 0b0<<23) // MCLKSEL, PBCLK is used by the Baud Rate Generator
               ;
  
  Specifically for this discussion, notice STXISEL<1:0> of SPIxCON == '00' (SPIxTXIF is set when the last transfer is shifted out of SPISR and transmit operations are complete)
• call SPI_xfer( p_dst, len ) where p_dst is RAM address to write to, and len is number of bytes to read.
• load len bytes into transmit FIFO SPIxTXB by consecutively writing each byte to SPIxBUF (len < 16)
• clear SPIxTXIF
• wait for all SPIxTXB bytes to be moved to SPIxSR and shifted out, and all bytes shifted into SPIxSR and moved into SPIxRXB.   Since received data might be less than 16 bytes, I thought I could use SPIxTXIF assertion,which means all transmit bytes have been shifted out of SPIxSR,and (I assumed) all receive bytes shifted into SPIxSR and moved into SPIxRXB).
• read bytes from SPIxBUF and write to p_dst until SPIxSTAT.SPIRBE == 0.
  

But apparently I am wrong at step 5!   At the moment SPIxTXIF asserts, not all bytes are received into SPIxRXB!
Instead, the only way (I can find) to positively know all expected bytes are received is to repeatedly poll SPIxSTAT.RXBUFELM until the value matches the number of bytes transmitted.  

Is there a better method that could use an interrupt?  (I'm thinking of how to use DMA for this process).