如何解决SP-6和Vref生成的DDR SDRAM终端方案?

只是为了获取信息，如果我使用了spartan-3那么我应该使用外部并行和串联终端来进行DQ＆amp;
地址线的DQSand并行端接如io看到的inSP3 PCIe启动器原理图....
对于Spartan 3到单个DDR1（即点对点），我建议：
信号FPGA端DRAM端
DQ，DQS，DM外部串联和并联外部串联和并联
A，BA，控制外部串联外部并联
假设50欧姆走线，串联电阻应为25欧姆，并联电阻为50欧姆（至VTT）。
该设置将起作用，即使是很长的痕迹。
如果可以缩短走线，则可以减少对端接电阻的需求 - 可以安全地降低串联电阻的值，并且可以安全地增加并联电阻的值。
在迹线极短的情况下，串联并联电阻可以增加到无穷大（未加载），串联电阻可以减小到零（短路）。
在这种情况下，“极短”意味着：“波长在其上升或下降时间内行进的距离远小于三分之一”，例如对于400 ps上升的信号和沿着150 mm / ns的迹线行进的下降时间“非常
短“意味着远小于20毫米，所以我预测10毫米将没有终止会很好。
其次，我已经改变主意，将DDR2 SDRAM与SP6一起使用，因为有库存的可用性，幸运的是，我之前没有意识到。
DDR2具有数据线的片上终端，使终端更容易。
正如Bob指出的那样，为什么不使用DDR3呢？
它们的价格几乎合理：
http://www.digikey.com/product-detail/en/W631GG6KB-15/W631GG6KB-15-ND/3124559
所以我现在得出的结论是，我只需要在地址，RAS，CAS和WE引脚上只有50欧姆并联端接（外部），如某些原理图所示。
DQ / DQS将以并行方式在FPGA内部终止（我猜）。
对于Spartan 6到单个DDR2或DDR3（即点对点），我建议：
信号FPGA端DRAM端
DQ，DQS，DM内部串联和并联内部串联和并联
A，BA，控制内部系列无
如果您不关心功耗，并联电阻应与走线阻抗相同（SI最安全），如果功率很重要，那么只要走线长度短和/或串联电阻，就可以增加并联电阻
增加了。
默认串联电阻值为：
SSTL2（2V5，DDR）：25欧姆
SSTL18（1V8，DDR2）：20欧姆
SSTL15（1V5，DDR3）：34欧姆
如果减弱或省去并联终端，则可以将这些值增加到跟踪阻抗附近。
对于我最近的S6 DDR3项目，我将DDR3设置为40欧姆串联电阻和40欧姆并联电阻，S6设置为25欧姆串联电阻和75欧姆并联电阻。
使用的传输线为40欧姆。
有关我的S6终止设置的详细信息，请参见此处的UCF文件：
http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/56
此外，我应该使用哪个工具来模拟FPGA和DDR / DDR / DDR3接口......有没有免费的？
一种流行的商业工具是HyperLynx，价格昂贵。
一个仍然非常有用的免费工具是Spice。
您可以使用Spice中的传输线的瞬态仿真很好地模拟这种类型的信号。
最好的祝福，
斯蒂芬
在原帖中查看解决方案



以下为原文

just for information if i had used spartan-3 then should i have used the external parallel and series termination for the DQ & DQS and parallel termination for the address lines as io saw in SP3 PCIe starter schematic ....
 
For Spartan 3 to a single DDR1 (ie point to point) I recommend:
 
Signal                      FPGA end                                  DRAM end
DQ,DQS,DM           external series and parallel   external series and parallel
A,BA,control            external series                          external parallel
 
Assuming 50 ohm traces the series resistors should be 25 ohms and the parallel resistors 50 ohms (to VTT).
That setup will work, even for quite long traces.  If the traces can be made shorter then the need for the termination resistors reduces - the series resistors can safely be reduced in value and the parallel resistors can safely be increased in value.  In the case where the traces are extremely short the series parallel resistors can be increased to infinity (not loaded) and the series resistors can be reduced to zero (shorted out). "extremely short" in this case means: "much less than one third of the distance the wave can travel in its rise or fall time" eg for a signal with 400 ps rise and fall times travelling along a trace at 150mm per ns "extremely short" means much less than 20mm, so I predict 10mm would be fine without termination.
 
secondly i have changed my mind to use the DDR2 SDRAM with SP6 due to availability in stock fortunately, i was unaware of earlier.
 
DDR2 have On Die Termination for the data lines, which makes termination easier.
As Bob has pointed out though, why not use DDR3 ?  They are available at an almost reasonable price:
 
http://www.digikey.com/product-detail/en/W631GG6KB-15/W631GG6KB-15-ND/3124559
 
So what i conclude now that i need only 50 Ohm parallel termination (external) on the address, RAS,CAS and WE pins only as seen in some schematics. DQ/DQS will be terminated internally in FPGA in a parallel fashion (i guess).
 
For Spartan 6 to a single DDR2 or DDR3 (ie point to point) I recommend:
 
Signal                      FPGA end                                  DRAM end
DQ,DQS,DM           internal series and parallel   internal series and parallel
A,BA,control            internal series                          none
 
If you don't care about power dissipation the parallel resistors should be the same as the trace impedance (safest for SI), if power matters then the parallel resistors can be increased as long as the trace length is short and/or the series resistors are increased.
Default series resistors values are:
SSTL2 (2V5,DDR): 25 ohms
SSTL18 (1V8,DDR2): 20 ohms
SSTL15 (1V5,DDR3): 34 ohms
These values can be increased up to around the trace impedance if the parallel termination is weakened or dispensed with.
 
For my most recent S6 DDR3 project I set up the DDR3 for 40 ohms series resistance and 40 ohms parallel resistance and the S6 for 25 ohms series resistance and 75 ohms parallel resistance.  The transmission lines used are 40 ohms.
Full details of my S6 termination settings can be seen from the UCF file here:
 
http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/56
 
Moreover which tool should i use for simulation of the FPGA and DDR/DDR/DDR3 interface...is there any available free of cost ??
 
A popular commercial tool is HyperLynx, which is expensive.  
A free tool that can still be very useful is Spice.  You can model this type of signalling quite well using transient simulation of transmission lines in Spice.
 
Best regards,
Stephen
 
View solution in original post

我想知道当DDR SDRAM（使用SSTL2）与spartan-6或串联终端接口时，我们是否只需要并行终端...
我的意见：
双向DQ，DQM和DQS（选通）线：片上终结
差分时钟：并行终端。
地址/控制组：并行或串行终止
该建议特别适用于Spartan-6 MIG / MCB设计，因为Spartan-6 MCB不支持多个存储器件，并且所有接口信号（通过构造）都是2针点对点信号线。
您的里程可能会有所不同，无法保证，模拟电路仿真是您的责任。
（对没有正式法律培训的人来说也不错！）
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
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以下为原文

i want to know that do we need only parallel termination when interfacing DDR SDRAM (using SSTL2) with spartan-6 or series termination...
 
My opinions:

• Bidirectional DQ, DQM, and DQS (strobe) lines:  on-die termination
  
• Differential clock:  parallel termination.
  
• Address/control groups:  either parallel or series termination
  

This advice applies specifically to Spartan-6 MIG/MCB designs, because Spartan-6 MCB does not support more than a single memory device, and all interface signals are (by construction) 2-pin point-to-point signal lines.
 
Your mileage may vary, no guarantees, and analogue circuit simulation is your responsibility. (not bad for someone with no formal legal training!)
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

目前尚不清楚你对“片上终结”的意思，这通常是指网络的内存端。
我不知道DDR（原始而不是DDR2）部件上的ODT。
2.5V SSTL2似乎意味着更老
一代回忆。
除非你有其他迫切的需要使用“原始”DDR SDRAM，我建议使用
较新的系列（DDR2或DDR3）可以在提高功率的同时实现更高的传输速率。
如果你的
推理是使用银行的其余部分用于其他2.5V I / O，然后我会考虑你是否可以
将那些少数剩余引脚的IO标准改为1.8 V或更低的Vcco。
-  Gabor
-  Gabor



以下为原文

It's not clear what you mean about "on-die termination" which usually refers to the memory end of the net.
I was not aware of ODT on DDR (original not DDR2) parts. The 2.5V SSTL2 seems to imply the older
generation memories.
 
Unless you have some other pressing need to use "original" DDR SDRAM, I would suggest using a
newer family (DDR2 or DDR3) which will save power while allowing higher transfer rates.  If your
reasoning is to use the remainder of the bank for other 2.5V I/O, then I'd look at whether you could
change the IO standards for those few remaining pins to work at 1.8V or lower Vcco.
 
-- Gabor
-- Gabor

我之前已经将Spartan 6连接到DDR SDRAM，看看我的原理图和UCF文件：
http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/48
我采用的方法主要使用Spartan 6内置终端，时钟的DRAM端只有3个外部电阻和DQS信号。
鲍勃写道：
>我的意见：
>双向DQ，DQM和DQS（选通）线：片内终结>差分时钟：并行终端。
>地址/控制组：parallelorseries终止
我使用的方案是： 
FPGA端DRAM端
DQ，DQM：系列和并行无
DQS：串联和并联（使用分立电阻）
diff clock：none parallel（使用分立电阻）
地址/控件：系列无
所有FPGA终端均使用Spartan 6内部未调整终端。
>此外，我可以从稳压器产生2.5V电压，并使用Vref的简单分压电路产生VTT
>和终端电阻。
不要那样做！
您需要比分压器提供更好的负载调节，特别是对于VTT。
TI TPS51100表现良好，或者如果您想要更便宜的替代品，请使用RichTek RT9026。
Stephen EcobSilicon On InspirationSydney Australia www.sioi.com.auSpartan 6 LX75，带2GB DDR3 DIMM，售价375美元：http：//www.sioi.com.au/shop/product_info.php/cPath/24/products_id/56



以下为原文

I've interfaced a Spartan 6 to DDR SDRAM before, take a look at my schematic and UCF file:
 
http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/48
 
The approach I took mainly uses the Spartan 6 built in termination, with just 3 external resistors at the DRAM end of the clock and DQS signals.
 
Bob wrote:
> My opinions:
> Bidirectional DQ, DQM, and DQS (strobe) lines:  on-die termination
> Differential clock:  parallel termination.
> Address/control groups:  either parallel or series termination
 
The scheme I used is:
                               FPGA end                                                DRAM end
DQ,DQM:              series and parallel                               none
DQS:                     series and parallel                                parallel (using discrete resistors)
diff clock:              none                                                          parallel (using discrete resistor)
Addr/control:        series                                                       none
 
All of the FPGA end termination uses Spartan 6 internal untuned termination.
 
> moreover can i generate 2.5V from a regulator and generate VTT using a simple voltage divider circuit for Vref
> and terminator resistors.
 
Don't do that!  You need much better load regulation than a voltage divider provides, especially for VTT.
A TI TPS51100 does it well, or use a RichTek RT9026 if you want a cheaper alternative.
 
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
Spartan 6 LX75 with 2GB DDR3 DIMM for $375:
http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/56
 

目前尚不清楚你对“片上终结”的意思，这通常是指网络的内存端。
我不知道DDR（原始而不是DDR2）部件上的ODT。
2.5V SSTL2似乎意味着更老
一代回忆。
谢谢，Gabor。
你是对的。
请忽略我以前的帖子。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
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以下为原文

It's not clear what you mean about "on-die termination" which usually refers to the memory end of the net.
I was not aware of ODT on DDR (original not DDR2) parts. The 2.5V SSTL2 seems to imply the older
generation memories.
 
Thank you , Gabor.  You are correct.  Please ignore my previous post.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

亲爱的斯蒂芬
非常感谢您宝贵的建议和建议以及参考原理图...仅供参考，如果我使用的是spartan-3那么我应该使用DQ＆amp;的外部并行和串联终端。
地址线的DQSand并行端接如io看到的inSP3 PCIe启动器原理图....
其次，我已经改变主意，将DDR2 SDRAM与SP6一起使用，因为有库存的可用性，幸运的是，我之前没有意识到。
所以我现在得出的结论是，我只需要在地址，RAS，CAS和WE引脚上只有50欧姆并联端接（外部），如某些原理图所示。
DQ / DQS将以并行方式在FPGA内部终止（我猜）。
但是为什么Micron文档（“用于点对点系统设计的H / W技巧”，TN4614，第11页）说只有在满足以下条件之一时才需要并行终止
1.五个或更多DDR设备
2.> 2in走线长度
3.模拟结果差
4.原型制作期间的单位或多位错误（模拟后）
如果以上都不是真的怎么办？如果按照同一微米文件的第10页所解释的那样，我应该通过命中和试验进行系列终止。
此外，我应该使用哪个工具来模拟FPGA和DDR / DDR / DDR3接口......有没有免费的？
最好的祝福
矩阵



以下为原文

Dear stephen
 
thanks a lot for your valuable suggestions and recommmendations and reference schematic... just for information if i had used spartan-3 then should i have used the external parallel and series termination for the DQ & DQS and parallel termination for the address lines as io saw in SP3 PCIe starter schematic ....
secondly i have changed my mind to use the DDR2 SDRAM with SP6 due to availability in stock fortunately, i was unaware of earlier.
 
So what i conclude now that i need only 50 Ohm parallel termination (external) on the address, RAS,CAS and WE pins only as seen in some schematics. DQ/DQS will be terminated internally in FPGA in a parallel fashion (i guess). BUT WHY then a Micron document ("H/W tips for point to point system design", TN4614, page 11) says that parallel termination is only required  when at least one of the following is true
1. five or more DDR devices
2. >2in trace lengths
3. poor simulation results
4. single or multibit error during prototyping (after simulation)
 
What if none of the above is true Should i go for series termination by hit and trial as explained on page 10 of the same micron document.
Moreover which tool should i use for simulation of the FPGA and DDR/DDR/DDR3 interface...is there any available free of cost ??
 
best regards
 
matrix

我没有阅读（或重读）Micron TNR文档，但您可以轻松地将您的摘要解释如下：
除非替代方案不起作用，否则您不需要使用并行终止。
或者，更简洁......
除非需要使用并行终端，否则不需要使用并行终端。
需要明确的是：考虑使用并行终端的四个理由列表可能与并行终止有关，也可能没有。
让我们一个接一个......
1.五个或更多DDR设备
如果所有五个（或更多）设备彼此非常靠近，则使用串联终端可能没有问题。
但通常更多的负载引脚意味着某些负载引脚距离跟踪端点更远，因此信号稳定时间将受到影响。
对于时钟信号（任何边沿激活的信号），不应考虑对具有多个负载引脚的线路使用串联终端。
2.> 2in走线长度
对于单个负载引脚，跟踪长度对于正确设计的串联端接信号线无关紧要。
这是每天完成的，结果非常可靠。
3.模拟结果差
有很多方法可以很好地设计信号迹线，有或没有并联端接。
话虽如此，电路仿真结果可用于表明并行端接对您的设计更有效 - 通常是因为您的设计的某些方面不适合串联端接。
4.原型制作期间的单位或多位错误（模拟后）
与＃3相同的答案在这里适用：有很多方法可以很好地设计信号迹线，有或没有并行端接。
＃4的要点是，您可以跳过电路仿真的时间，麻烦和费用，并通过构建电路板并对其进行测试，发现您的设计不可靠。
只是为了澄清：实际上没有非终止信号线这样的东西。
输出驱动器本身具有非零输出阻抗，可为其驱动的信号线提供串联端接。
所以“未终止”线是串联终止的一种形式。
根据具体细节，驱动器的阻抗可能足以匹配可靠的串联终端解决方案。
驱动器阻抗不匹配的程度将导致振铃或建立时间增加。
你读过这个帖子吗？
它可能对你有帮助......
下一个问题：为什么选择DDR2而不是DDR3？
如果这是一种生产意图设计，DDR2可能会在不久的将来变得比DDR3设备更昂贵，更少可用。
几年前达到了DDR2到DDR3的交叉点。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

I did not read (or re-read) the Micron TNR doc, but you might easily paraphrase your summary as follows:
 
You don't need to use parallel termination unless the alternatives do not work.
 
or, more succinctly...
 
You don't need to use parallel termination unless you need to use parallel termination.
 
Just to be clear:  the list of four reasons to consider using parallel termination may or may not have anything to do with parallel termination.  Let's take these one by one ...
 
1. five or more DDR devices
 
If all five (or more) devices are located very close to each other, there may not be a problem using series termination.  But usually more load pins means that some load pins are more distant from the trace endpoint, and signal settling time will suffer as a result.
 
For clock signals (any signal which is edge-active), you should not consider using series termination for lines with more than a single load pin.
 
2. >2in trace lengths
 
With a single load pin, trace length should not matter for a properly designed series-terminated signal line.  This is done every day with utterly reliable results.
 
3. poor simulation results
 
There are plenty of ways to poorly design a signal trace, with or without parallel termination.  Having said that, circuit simulation results can be used to suggest that parallel termination will work better for your design -- usually because of some aspect of your design is unsuitable for series termination.
 
4. single or multibit error during prototyping (after simulation)
 
Same answer as #3 applies here:  there are plenty of ways to poorly design a signal trace, with or without parallel termination.  The point of #4 is that you can skip the time, trouble, and expense of circuit simulation and find that your design is unreliable simply by building the board and testing it.
 
Just to clarify:  In practice there is no such thing as non-terminated signal lines.  The output driver itself has a non-zero output impedance which contributes series termination to the signal line it is driving.  So "unterminated" line is a form of series termination.  Depending on specific details, the driver's impedance may be a good enough match for a reliable series-termination solution.  The extent to which the driver's impedance is not a good match will contribute to increased ringing or settling time.
 
Have you read this thread?  It might be helpful to you...
 
Next question:  Why choose DDR2 over DDR3?  If this is a production-intent design, DDR2 is likely to become more expensive and less available than DDR3 devices in the near future.  The crossover point for DDR2 to DDR3 was reached several years ago.
 
-- Bob Elkind
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非常感谢，鲍勃。
实际上这是一个开发板，我想体验DDR2，因为我们以前从未使用它，可能会用于即将推出的主板。
我只使用一个带有斯巴达-6 MCB bank3的IS43DR16640A-3DBL（DDR2,64M X 16）。
所以我现在计划在地址线上使用并联电阻（用于更安全的设计），在数据和选通线上使用“0”欧姆串联电阻来替换它们（如果需要的话）。
显然我在这个特定情况下得出的结论是，我可以将内部FPGA终端用于数据/选通线，并将地址线与任何串联/并联电阻连接（对于位于FPGA附近的单个芯片）。
此外，我的主板上有100 / 96MHz和不同的200MHz晶振，并计划在333MHz至400MHz使用它。
据我所知，如果使用MIG创建设计并通过MCB实现设计，FPGA将生成适当的时钟。
我如何使用IBIS模型来模拟我的场景。
最好的祝福
矩阵



以下为原文

 
thanks a lot, bob.
this is a development board actually and i want to experience DDR2 as we have never used it before and may be used in upcoming boards. i am using only one IS43DR16640A-3DBL (DDR2, 64M X 16) with spartan-6 MCB bank3. so what i am planning now to have parallel resistors (for safer design) on the address lines and "0" ohm series resistors on the data and strobe lines to replace them with optimal ones (if in case i need them).
apparently what i figure out in this specific case is that i can use internal FPGA termination for data/strobe lines and connect address lines with out any series/parallel resistors (for a single chip located near the FPGA).
 
moreover i have 100/96MHz and a differntial 200MHz crystal on my board and plan to use it at 333MHz to 400 MHz. what i understand uptil now that FPGA will generate proper clock if a design is created using MIG and implemented thru MCB.
how can i use IBIS models to simulate my scenario.
 
best regards
 
matrix

只是为了获取信息，如果我使用了spartan-3那么我应该使用外部并行和串联终端来进行DQ＆amp;
地址线的DQSand并行端接如io看到的inSP3 PCIe启动器原理图....
对于Spartan 3到单个DDR1（即点对点），我建议：
信号FPGA端DRAM端
DQ，DQS，DM外部串联和并联外部串联和并联
A，BA，控制外部串联外部并联
假设50欧姆走线，串联电阻应为25欧姆，并联电阻为50欧姆（至VTT）。
该设置将起作用，即使是很长的痕迹。
如果可以缩短走线，则可以减少对端接电阻的需求 - 可以安全地降低串联电阻的值，并且可以安全地增加并联电阻的值。
在迹线极短的情况下，串联并联电阻可以增加到无穷大（未加载），串联电阻可以减小到零（短路）。
在这种情况下，“极短”意味着：“波长在其上升或下降时间内行进的距离远小于三分之一”，例如对于400 ps上升的信号和沿着150 mm / ns的迹线行进的下降时间“非常
短“意味着远小于20毫米，所以我预测10毫米将没有终止会很好。
其次，我已经改变主意，将DDR2 SDRAM与SP6一起使用，因为有库存的可用性，幸运的是，我之前没有意识到。
DDR2具有数据线的片上终端，使终端更容易。
正如Bob指出的那样，为什么不使用DDR3呢？
它们的价格几乎合理：
http://www.digikey.com/product-detail/en/W631GG6KB-15/W631GG6KB-15-ND/3124559
所以我现在得出的结论是，我只需要在地址，RAS，CAS和WE引脚上只有50欧姆并联端接（外部），如某些原理图所示。
DQ / DQS将以并行方式在FPGA内部终止（我猜）。
对于Spartan 6到单个DDR2或DDR3（即点对点），我建议：
信号FPGA端DRAM端
DQ，DQS，DM内部串联和并联内部串联和并联
A，BA，控制内部系列无
如果您不关心功耗，并联电阻应与走线阻抗相同（SI最安全），如果功率很重要，那么只要走线长度短和/或串联电阻，就可以增加并联电阻
增加了。
默认串联电阻值为：
SSTL2（2V5，DDR）：25欧姆
SSTL18（1V8，DDR2）：20欧姆
SSTL15（1V5，DDR3）：34欧姆
如果减弱或省去并联终端，则可以将这些值增加到跟踪阻抗附近。
对于我最近的S6 DDR3项目，我将DDR3设置为40欧姆串联电阻和40欧姆并联电阻，S6设置为25欧姆串联电阻和75欧姆并联电阻。
使用的传输线为40欧姆。
有关我的S6终止设置的详细信息，请参见此处的UCF文件：
http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/56
此外，我应该使用哪个工具来模拟FPGA和DDR / DDR / DDR3接口......有没有免费的？
一种流行的商业工具是HyperLynx，价格昂贵。
一个仍然非常有用的免费工具是Spice。
您可以使用Spice中的传输线的瞬态仿真很好地模拟这种类型的信号。
最好的祝福，
斯蒂芬



以下为原文

just for information if i had used spartan-3 then should i have used the external parallel and series termination for the DQ & DQS and parallel termination for the address lines as io saw in SP3 PCIe starter schematic ....
 
For Spartan 3 to a single DDR1 (ie point to point) I recommend:
 
Signal                      FPGA end                                  DRAM end
DQ,DQS,DM           external series and parallel   external series and parallel
A,BA,control            external series                          external parallel
 
Assuming 50 ohm traces the series resistors should be 25 ohms and the parallel resistors 50 ohms (to VTT).
That setup will work, even for quite long traces.  If the traces can be made shorter then the need for the termination resistors reduces - the series resistors can safely be reduced in value and the parallel resistors can safely be increased in value.  In the case where the traces are extremely short the series parallel resistors can be increased to infinity (not loaded) and the series resistors can be reduced to zero (shorted out). "extremely short" in this case means: "much less than one third of the distance the wave can travel in its rise or fall time" eg for a signal with 400 ps rise and fall times travelling along a trace at 150mm per ns "extremely short" means much less than 20mm, so I predict 10mm would be fine without termination.
 
secondly i have changed my mind to use the DDR2 SDRAM with SP6 due to availability in stock fortunately, i was unaware of earlier.
 
DDR2 have On Die Termination for the data lines, which makes termination easier.
As Bob has pointed out though, why not use DDR3 ?  They are available at an almost reasonable price:
 
http://www.digikey.com/product-detail/en/W631GG6KB-15/W631GG6KB-15-ND/3124559
 
So what i conclude now that i need only 50 Ohm parallel termination (external) on the address, RAS,CAS and WE pins only as seen in some schematics. DQ/DQS will be terminated internally in FPGA in a parallel fashion (i guess).
 
For Spartan 6 to a single DDR2 or DDR3 (ie point to point) I recommend:
 
Signal                      FPGA end                                  DRAM end
DQ,DQS,DM           internal series and parallel   internal series and parallel
A,BA,control            internal series                          none
 
If you don't care about power dissipation the parallel resistors should be the same as the trace impedance (safest for SI), if power matters then the parallel resistors can be increased as long as the trace length is short and/or the series resistors are increased.
Default series resistors values are:
SSTL2 (2V5,DDR): 25 ohms
SSTL18 (1V8,DDR2): 20 ohms
SSTL15 (1V5,DDR3): 34 ohms
These values can be increased up to around the trace impedance if the parallel termination is weakened or dispensed with.
 
For my most recent S6 DDR3 project I set up the DDR3 for 40 ohms series resistance and 40 ohms parallel resistance and the S6 for 25 ohms series resistance and 75 ohms parallel resistance.  The transmission lines used are 40 ohms.
Full details of my S6 termination settings can be seen from the UCF file here:
 
http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/56
 
Moreover which tool should i use for simulation of the FPGA and DDR/DDR/DDR3 interface...is there any available free of cost ??
 
A popular commercial tool is HyperLynx, which is expensive.  
A free tool that can still be very useful is Spice.  You can model this type of signalling quite well using transient simulation of transmission lines in Spice.
 
Best regards,
Stephen
 

嗨，我很困惑，因为我也找到了这个页面，http：//www.xilinx.com/support/answers/38651.htm#linkedARRecords。
对于SP6和DDR RAM的组合，可以使用内部终端吗？
具体原因是，对于DQS和CLK引脚，是否需要外部端接？
谢谢



以下为原文

Hi, I got confused because I also found this page, http://www.xilinx.com/support/answers/38651.htm#linkedARRecords.
For the conbination of SP6 and DDR RAM, can the internal termination be used? What is the particular reason, that for DQS and CLK pins the external terminations are requried?
 
Thanks