内存PCB设计用三个地平面层是不是有点超大？

嗨，
你确定你在提到UG488吗？
有关Spartan-6和DDR3 PCB导轨部分，请参阅UG388-第41-43页
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
我看到声明“数据组应该引用GROUND平面”。
也存在于UG388中。
我相信所有DQ信号都应该在一层中进行路由，以便具有相同的＆amp;
并行走线长度，以避免串扰，并有更好的时序和
更好的SI。
如果您在三个不同的平面中布线，并且有三个不同的地平面，我不确定所有三个层的闭环是否表现相同，并且可能会引入偏斜，并通过降低最大频率支持。
请查看以下PDF地面和动力平面部分，它们可以帮助您获得良好的概念
http://www.ti.com/lit/an/scaa082/scaa082.pdf
如果你不能重新设计，我认为最好去IBIS模拟并以较低的频率运行设计。
希望这可以帮助
问候，
Vanitha。
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在原帖中查看解决方案



以下为原文

Hi,
 
Are you sure you are referring UG488?
For Spartan-6 and DDR3 PCB guideliness section please refer UG388 -page 41-43
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
 
 
I see the statement  "A data group should be referenced to a GROUND plane."  exists in UG388 as well.
I believe all DQ signals should be roued in one layer inorder to have equal &  parallel  trace lengths, to avoid cross talk and to have better timing &  better SI.  If  you route in three different planes ad have three different ground planes I am not sure if  closed loop of all the three layers behave the same way and might introduce skew and there by reduce maximum frequency support.
 
Please check below PDF Ground and Power plane section which might help you with good concepts
http://www.ti.com/lit/an/scaa082/scaa082.pdf
 
 If you can't redesign, I think better to do go IBIS simulations and run the design at  lower frequencies.
 
Hope this helps
 
Regards,
Vanitha.
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View solution in original post

嗨，
你确定你在提到UG488吗？
有关Spartan-6和DDR3 PCB导轨部分，请参阅UG388-第41-43页
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
我看到声明“数据组应该引用GROUND平面”。
也存在于UG388中。
我相信所有DQ信号都应该在一层中进行路由，以便具有相同的＆amp;
并行走线长度，以避免串扰，并有更好的时序和
更好的SI。
如果您在三个不同的平面中布线，并且有三个不同的地平面，我不确定所有三个层的闭环是否表现相同，并且可能会引入偏斜，并通过降低最大频率支持。
请查看以下PDF地面和动力平面部分，它们可以帮助您获得良好的概念
http://www.ti.com/lit/an/scaa082/scaa082.pdf
如果你不能重新设计，我认为最好去IBIS模拟并以较低的频率运行设计。
希望这可以帮助
问候，
Vanitha。
--------------------------------------------------
-------------------------------------------请在发布前进行谷歌搜索，
您可能会找到相关信息。请留下帖子 - “接受为解决方案”，如果提供的信息有用且回复，请给予赞誉



以下为原文

Hi,
 
Are you sure you are referring UG488?
For Spartan-6 and DDR3 PCB guideliness section please refer UG388 -page 41-43
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
 
 
I see the statement  "A data group should be referenced to a GROUND plane."  exists in UG388 as well.
I believe all DQ signals should be roued in one layer inorder to have equal &  parallel  trace lengths, to avoid cross talk and to have better timing &  better SI.  If  you route in three different planes ad have three different ground planes I am not sure if  closed loop of all the three layers behave the same way and might introduce skew and there by reduce maximum frequency support.
 
Please check below PDF Ground and Power plane section which might help you with good concepts
http://www.ti.com/lit/an/scaa082/scaa082.pdf
 
 If you can't redesign, I think better to do go IBIS simulations and run the design at  lower frequencies.
 
Hope this helps
 
Regards,
Vanitha.
---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

亲爱的Vanitha
谢谢你的快速回报。
我和PCB设计师谈过并告诉我，为了将每个数据信号放在同一层，他应该交换一些线路。
根据UG388（而不是488 ......）和bob elkind的帖子，这是可能的。
所以我想知道我是否转换，让DQ0说DQ0，我是否必须对我的VHDL代码做任何事情，比如在UCF文件上更改引脚位置？
谢谢
弗朗索瓦



以下为原文

Dear Vanitha
 
Thank you for your really quick repply.
I talked with the PCB designer and told me that to put every Data signals on the same layer he should swapp some lines. According UG388 (and not 488...) and bob elkind post, it is possible.
So I am wondering if I swapp, lets say DQ0 with DQ2, will I have to do anything on my VHDL code like change pin location on UCF file?
 
Thanks
François

嗨，
在Spartan6中，无需在ucf中执行任何操作，因为MCB是硬块，所有DQ引脚都是固定的。
但是你可以在内存端交换它们，正如鲍勃在另一篇文章中所说的那样
问候，
Vanitha
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以下为原文

Hi,
 
In Spartan6 no need to do any cahnges in ucf as MCB is hard block all DQ pins are fixed.
However you can swap them at memory end as said by Bob in the other post
 
 
Regards,
Vanitha
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bouscasse写道：
亲爱的大家
我们目前正在使用斯巴达6（XC6LX25）和微米DDR3设计项目的PCB。
UG488指南第41页告诉：“数据组应该参考GROUND平面。”
目前，数据信号在三个不同的层上路由。
如果我正确理解了这个指南，我们应该将一个地平面与每个层相关联，并附有数据信号。
在我的情况下，三个地平面层...是不是有点超大？
为什么这个指南适合？
隔离？
通常，您必须路由与参考平面相邻的所有信号，参考平面通常是地平面，但电源平面也可用作参考平面。
如果你有四个信号路由层，你将有一个八层叠加：
1）信号顶部
2）地面
3）信号内部1
4）地面
5）电力
6）信号内部2
7）地面
8）信号底部
有时两个内层可以是电源层，或者其他平面中的一个可能是电源层。
取决于电力系统的复杂性。
我们的想法是，通过高速信号传输，信号走线的返回电流将位于信号正下方（或顶部）的相邻平面内。
----------------------------是的，我这样做是为了谋生。



以下为原文

bouscasse wrote:
Dear all
 
We are currently designing the PCB of a project using a spartan 6 (XC6LX25) and a micron DDR3.
Guidelines page 41 of UG488 tell: "A data group should be referenced to a GROUND plane."
Currently data signals are routed on three differents layers. If I understand correctly this guideline, we should associate one ground plane to each layer with data signal. In my case three ground plane layers... Isn't it a little bit over-sized? Why is this guideline for? Isolation?

In general, you must route all signals adjacent to a reference plane, which is usually a ground plane, but a power plane functions as a reference plane too. If you have four signal routing layers, you will have an eight-layer stackup: 
 
1) signal top
2) ground
3) signal inner 1
4) ground
5) power
6) signal inner 2
7) ground
8) signal bottom
 
sometimes the two inner layers can be power layers, or perhaps one of the other planes is a power plane. Depends on the complexity of the power system.
 
The idea is that with high-speed signaling, the return current for a signal trace will be in the adjacent plane directly underneath (or on top of) the signal. 
----------------------------Yes, I do this for a living.

谢谢vanitha和贝斯曼。
PCB设计人员正试图将所有数据信号放在同一层上。
Bassman我对你的解决方案感到有些惊讶，仍然根据UG388，信号应该在内部层路由。
你知道为什么吗？
这真的很重要吗？
Vanitha我不知道如何进行IBIS模拟。
你有推荐给我的软件或“起点”吗？
你们都在谈论高频率。
哪个值是“高频率”？
我如何确定DQS频率？
（我所有的输入MIG的时钟都是200MHz）
弗朗索瓦



以下为原文

Thank you vanitha and bassman.
The PCB designer is trying to put all the Data signals ont the same layer.
 
Bassman I am little bit surprised by your solution, still according to UG388, signal should be routed in the internall layers. Do you know why? Is it really important?
 
Vanitha I don't know how to perform IBIS simulation. Do you have a software or "starting point" to recomend to me?
 
You are both talking about high frequency. Up to which value is "high frequency"? How may I determine DQS frequency? (All my input MIG's clocks are 200MHz)
 
François
 
 

我刚刚重新提出有关时钟频率的问题：
根据UG388的第38页，有两个频率，clkin1频率（在我的情况下是200MHz）和sys_clk2x频率（所以400MHz）。
我对吗？
数据信号也是如此 
1 / clkin1frequency 
2 / sys_clk2x频率 
3 /它取决于/两者 
3 /我根本不了解时钟分布
谢谢
弗朗索瓦



以下为原文

I just reformulate my question about clock frequency:
According page 38 of UG388 there is two frequency, clkin1 frequency (200MHz in my case) and sys_clk2x frequency (so 400MHz). Am I right?
So is Data signals
    1/ clkin1 frequency 
    2/ sys_clk2x frequency
    3/ It depends/ Both
    3/ I didn't understand at all the clock distribution
 
 
Thank you
François

嗨，
内存以您在GUI中配置的频率运行，默认情况下Sysclk =内存频率。
由于这是DDR IO，因此对于LPDDR，可以采样两倍的内存频率.MIG支持的最大频率为200MHz。
因此数据速率为400Mbps。
对于IBIS模拟，请检查以下链接是否有助于您开始
http://www.xilinx.com/products/design_resources/signal_integrity/si_whyibis.htm
http://www.youtube.com/watch?v=xCJjY2YUWMc
http://www.sisoft.com/elearning/ibis-ami.html
问候，
Vanitha
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以下为原文

Hi,
 
Memory runs at the frequency that you configure in the GUI, by default Sysclk =  memory frequency.
As this is DDR IOs can be sampled at double the memory frequency for LPDDR max fequency supported by MIG is 200MHz.
So the data rate is 400Mbps.
 
For IBIS Simulations please check if below links help to give you a start
http://www.xilinx.com/products/design_resources/signal_integrity/si_whyibis.htm
 
http://www.youtube.com/watch?v=xCJjY2YUWMc
 
http://www.sisoft.com/elearning/ibis-ami.html
 
 
Regards,
Vanitha
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感谢您的澄清和链接。



以下为原文

Thank for this clarification and links.

bouscasse写道：
内部层。
你知道为什么吗？
这真的很重要吗？
这是带状线和微带线之间的区别，这进入了一些重型传输线理论。
去读一读。
你们都在谈论高频率。
哪个值是“高频率”？
我如何确定DQS频率？
（我所有的输入MIG的时钟都是200MHz）
实际上，频率是完全无趣的。
这是相关信号的边缘速率。
开始使用所有这些东西的好地方是约翰逊和格雷厄姆的书“高速数字设计”。
----------------------------是的，我这样做是为了谋生。



以下为原文

bouscasse wrote:
 
internall layers. Do you know why? Is it really important?

 It's the difference between stripline and microstrip, and this gets into some heavy-duty transmission-line theory. Go read up on it.

You are both talking about high frequency. Up to which value is "high frequency"? How may I determine DQS frequency? (All my input MIG's clocks are 200MHz) 

Actually, the frequency is completely uninteresting. it's the edge rate of the signals in question.
 
A good place to start with all of this stuff is Johnson and Graham's book, "High Speed Digital Design."
----------------------------Yes, I do this for a living.

谢谢巴斯曼。
我试着找这本书。
Vanitha我们最终没有成功将所有数据信号放在同一层，我们必须将它们分成两个不同的层。
弗朗索瓦



以下为原文

Thank you Bassman. I'l try to find this book.
Vanitha we finally didn't succeed to put all data signals in the same layer, we will have to route them in two different layers.
 
François