Spartan 3AN入门套件

我是FPGA编程的新手。
我正在使用Xilinx Spartan 3AN入门套件。
我正在尝试利用电路板上提供的模拟捕获电路将模拟信号（范围：0.4  -  2.9伏）转换为14位数字信号。
我在使ADC工作方面面临一些困难。
它始终提供0输出。
我为激活模拟捕获电路生成了以下信号：
1.产生一个6.25 MHz SPI_SCK时钟（来自50MHz板载时钟）
2.将增益设置为常数=“00010001”，当AMP_CS为低电平时，在8个SPI_SCK周期内将其作为SPI_MOSI串行发送到前置放大器。
3.在这8个SPI_SCK周期后，AMP_CS返回高电平。
然后，在每34个SPI_SCK周期后，周期性地产生宽度为5ns的AD_CONV脉冲。
5.我遗漏了AMP_SHDN和AMP_DOUT信号。
我没有得到ADC_OUT。
可能是什么问题？
我正在附加我的信号生成VHDL模块。
感谢致敬，
Sayak。
prescale.vhd 2 KB



以下为原文

I am new to FPGA programming. I am working with a Xilinx Spartan 3AN Starter Kit. I am trying to utilize the Analog Capture Circuit provided on the board for converting analog signal (range: 0.4 - 2.9 volts) to 14 bit digital signal.

I am facing some difficulties in making the ADC work. It is always providing a 0 output.

I have generated the following signals for activating the analog capture circuit:

1. Generated a 6.25 MHz SPI_SCK clock (from the 50MHz on-board clock)
2. Set the gain as a constant = "00010001", which is serially sent to the Pre-Amplifier as SPI_MOSI in 8  SPI_SCK cycles when AMP_CS is low.
3. After these 8 SPI_SCK cycles, the AMP_CS returns high.
4. Then AD_CONV pulse with a width of 5ns is generated periodically after every 34 SPI_SCK cycles.
5. I have left out the AMP_SHDN and AMP_DOUT signals.

I am not getting expted ADC_OUT. What may be the problem?

I am attaching my signal generation VHDL module.

Thanks and regards,
Sayak.
            prescale.vhd ‏2 KB