是否可以从表达式构建电路

您正在寻找的是VHDL或Verilog设计流程。
很少有人，主要是在过时的大学数字设计课程中，使用原理图。
ISE深入教程UG695涵盖了HDL设计流程。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
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以下为原文

What you are looking for is either a VHDL or Verilog design flow.  Very few people, mostly inside of antiquated college digital design courses, use schematics.  The ISE In-Depth Tutorial, UG695, covers HDL design flows.
------Have you tried typing your question into Google?  If not you should before posting.
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是的，我正在学习工程，我们正在使用fpga板和这个应用程序来构建和测试我们的电路。但我们用来构建卡诺图，找出表达式并使用logisim构建电路。现在我们开始使用fpga板
测试我们的电路，但我们不知道如何使用ISE从表达式构建电路......我对你的帖子不太了解。
你是说只有过时的学校使用表达式来构建电路？



以下为原文

Yes, I'm studying engineering and we are using fpga boards and this app to build and test our circuits.

But we used to build the karnaugh maps, figure the expressions out and build the circuit with logisim.

Now we started using the fpga boards to test our circuits but we don't know how to build circuits with ISE from expressions...

I didn't understood very well your post. Are you saying that only antiquated schools use expressions to build circuits???

psysc0rpi0n写道：是的，我正在研究工程，我们正在使用fpga板和这个应用程序来构建和测试我们的电路。但我们用来构建卡诺图，计算表达式并使用logisim构建电路。现在我们开始使用
fpga板测试我们的电路，但我们不知道如何使用ISE从表达式构建电路......
那么，你究竟在课堂上教授什么呢？
您的教授讲师是否教授任何针对FPGA的内容？
我不知道“Logisim”是什么。
我的帖子不太清楚。
你是说只有过时的学校使用表达式来构建电路？
他说，使用原理图输入来处理与FPGA有关的学校已经过时了，HDL是“使用表达式构建电路”的理想工具。
----------------------------是的，我这样做是为了谋生。



以下为原文

psysc0rpi0n wrote:
Yes, I'm studying engineering and we are using fpga boards and this app to build and test our circuits.

But we used to build the karnaugh maps, figure the expressions out and build the circuit with logisim.

Now we started using the fpga boards to test our circuits but we don't know how to build circuits with ISE from expressions...

So what, exactly, are you being taught in the class? Does your professor instructor teach anything specific to FPGAs? I don't know what "Logisim" is.

I didn't understood very well your post. Are you saying that only antiquated schools use expressions to build circuits???

He's saying that schools which use schematic entry for anything to do with FPGAs are antiquated, and that an HDL is the ideal tool for "using expressions to build circuits."
----------------------------Yes, I do this for a living.

>但我们过去常常构建卡诺图，将表达式计算出来并使用logisim构建电路。
这些是学习布尔代数和数字逻辑基础知识的精细作业，虽然我不知道logisim是什么，并假设它是某种类型的简单逻辑模拟器。
>现在我们开始使用fpga板来测试我们的电路
恕我直言，逐步学习以前的学习经验并将其应用于真实硬件几乎没有价值。
如果下一步是用FPGA推进数字设计知识，那么应该有使用HDL（VHDL或Verilog）的指令。
>你是说只有过时的学校使用表达式来构建电路？
我指的是那些仍然坚持要求使用原理图进行设计输入的数字实验室作业的学校。
这是20世纪80年代中期的主要设计风格，已被HDL设计方法所取代。
这相当于参加软件设计课程并被告知必须使用汇编而不是C，C ++，Java，Python等进行编程...
这是来自维基百科的快速卡诺地图示例及其布尔方程（您所指的是表达式）。
这就是Verilog模块
模块kmap（ 
输入A， 
输入B， 
输入C， 
输入D， 
输出F.
）;
分配F =（A＆amp;！C）|
（A＆amp;！B）|
（B和C＆安培;！d）;
endmodule
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> But we used to build the karnaugh maps, figure the expressions out and build the circuit with logisim.
 
These are fine assignments for learning the basics of boolean algebra and digital logic, although I have no idea what logisim is and assume that it is a simple logic simulator of some type.
 
> Now we started using the fpga boards to test our circuits
 
IMHO, taking the prior learning experience verbatim and applying it to real hardware has little value.   If the next step is to advanced the digital design knowledge with FPGAs then there should have been instruction in the use of HDL (either VHDL or Verilog).
 
> Are you saying that only antiquated schools use expressions to build circuits???
 
I was referring to schools that still insist on digital lab assignments that require the use of schematics for design entry.  This was the primary design style in mid-1980's and has been replaced with HDL design methods.  This would be the equivalent of taking a software design course and being told that you must program in assembly instead of C, C++, Java, Python, etc...
 
Here's a quick Karnaugh map example from Wikipedia and its boolean equation (what you are referring to as an expression).

 
And this is what it would be as a Verilog module
module kmap (   input A,   input B,   input C,   input D,   output F);assign F = (A&!C) | (A&!B) | (B&C&!D);endmodule 
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感谢您的解释...
在您的第一篇文章中，您了解了有关HDL / Verilog / VHDL实现的链接，对吧？
我只是不知道在哪里读...



以下为原文

Thanks for the explanation...
 
In your first post you gac«ve me a link to read about HDL/Verilog/VHDL implementation, right?
 
I just don't know where to read...

>我只是不知道在哪里读...
我提供了一个链接以及在之前的帖子中阅读的教程的确切文件名。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> I just don't know where to read...
 
I gave a link and the exact file name of the tutorial to read in the prior post.
------Have you tried typing your question into Google?  If not you should before posting.
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我一直在看那些文件，但我从那里学不到任何东西。
我正在寻找一个教程来帮助我，从开始，如何建立一个项目。
例：
我们第一次被教导做下面的事情：
去没有ISE菜单文件 - >新项目。
然后添加新源并选择原理图。
画出我们的电路。
然后添加New Source并选择Import new constrainst File（我猜选项名称是正确的，以添加ucf文件）并将输入和输出分配给fpga布局中的所需选项。
然后我们应该运行3个可以构建.bit文件的项目。
最后我们使用Digilent的Adept将这个.bit filo加载到fpga ...
现在，要构建一个使用VHDL / HDL / Verilog的项目，或者其他什么，我不知道程序！
干杯



以下为原文

I've been watchig those files but i can't learn anything from there. I was looking for a tutorial to help me, from the beggining, how to build a project.
 
Example:
 
We were taught the first time to do the follwoing:
 
Go no ISE menu File->New Project. Then Add New Source and choose schematic. Draw our circuit.
Then add New Source and choose Import new constrainst File (i guess the option name is correct to add the ucf file) and assign the inputs and outputs to the desired options in the fpga layout.
Then we should run 3  items that would build a .bit file.

Lastly we use Adept from Digilent to load this .bit filo into the fpga...
 
Now, to build a project to use VHDL/HDL/Verilog, or whatever, i don't know the procedure!!!
 
Cheers

>我正在寻找一个教程来帮助我，从开始，如何建立一个项目。
听起来你没有读过我之前提到过的UG695，因为第2章将对此进行详细介绍。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

>I was looking for a tutorial to help me, from the beggining, how to build a project.
 
It really sounds like you did not read UG695 that I refered to earlier as this is described in great detail in Chapter 2.
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对不起......我没看到第一个链接。
带有pdf文档的那个...我有点失明，因为我只能看到帖子底部的4个下载链接...
好吧，我会尝试阅读并理解教程......



以下为原文

I'm sorry... I didn't saw the first link. The one with the pdf document... I was kinda blind because i could only see the 4 download links that are in the bottom of your post...
 
Well, i'll try to read and understand the tutorial...