过度倾斜因为什么？

大家下午好，
我忙着使用UART进行RS485通信，现在我已达到4Mbit / s的速度。
这不是我想达到的目的。
现在，在执行Place＆amp;路线后，我有一个“过度倾斜因为”警告。
但是在“因为”之后我没有看到任何理由让我非常沮丧:)
我得到的完整警告如下：
警告：路由：455  -  CLK Net：UART / TRANSMITTER / BaudClk可能有过度偏斜，因为
现在我想在我修复此警告后，它还可以帮助我获得更好的时钟信号，这样我最终可以达到更快的速度。
我将在下面的代码中发布生成baudClock的代码。
我希望有人能指出我正确的方向。
常量DIV：整数：= ClockFreq / BaudRate;常量HALFDIV：整数：= DIV / 2;
BaudGen：进程（clk，reset）开始if（reset ='1'）然后 -  Reset Switch cval BaudClk elsif rising_edge（Clk）然后cval if（cval = HALFDIV）然后BaudClk cval结束if;
万一;
结束过程BaudGen;
现在我只有另一个进程，它可以在BaudClk的rising_edge上工作，我有一个状态机来创建startbit，data和stop bit。
那么有人能指出我的BaudClk生成器出错的方向吗？
提前致谢，
罗埃尔



以下为原文

Good Afternoon Everyone,

Im busy with a UART for a RS485 communication, unop now i reached speeds of like 4Mbit/s. This is not what i want to reach in the end.

Now i have a "excessive skew because" warning after executing the Place&route. But i dont see any reason after the "Because" which fustrates me a lot :)

The full warning i get is the following:
WARNING:Route:455 - CLK Net:UART/TRANSMITTER/BaudClk may have excessive skew because

Now i think after i fix this warning, it would also help me to get a better clock signal, so i can reach faster spedes eventually. I will post the code below where the baudClock is being generated. And i hope someone can give me a point in the right direction.

constant DIV : integer := ClockFreq / BaudRate;
constant HALFDIV : integer := DIV / 2;

BaudGen : process (clk,reset)
begin
     if (reset = '1') then
          -- Reset Switch
          cval <= 0;
          BaudClk <= '0';

     elsif rising_edge(Clk) then

          cval <= cval + 1;

          if (cval = HALFDIV) then

           BaudClk <= not BaudClk;
           cval <= 0;

           end if;
     end if;
end process BaudGen;



Now i only have another process wich works on the rising_edge of the BaudClkwhere i have a state machine to create the startbit, data and stop bit.

So can someone point me in the correct direction on what is going wrong in my BaudClk generator ?

Thanks in advance,
Roel