请问我必须使用第二个闪存或通过uC配置FPGA吗？

您的uC如何连接到用于FPGA配置的SPI闪存？
他们不能同时使用地址0。
如果电路板上有uC，为什么不使用uC配置FPGA？
将FPGA跳转到从串行配置模式，让uC从SPI存储器读取配置数据并将数据馈送到FPGA。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

How is your uC connected to the SPI flash memory used for FPGA configuration?  They cannot both be using address 0 for separate purposes.
 
If you have a uC on the board, why not use the uC to configure the FPGA?  Jumper the FPGA to slave serial config mode, and have the uC read the configuration data from the SPI memory and feed the data to the FPGA.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨，谢谢你的回答.. uC从地址0的SPI闪存启动。初始化uC后，我将释放SPI线并触发FPGA配置。
当然，FPGA必须从更高的地址加载此配置比特流。
这正是重点......当然，我可以通过我的uC读取比特流并配置FPGA，但这需要更长的时间，因为我必须对JTAG / SPI线进行bitbang。我的意思是，如果
FPGA可以自己获取其配置，而无需为JTAG花费额外的引脚，实现XSVF解释器等等，我仍然有可能用uC替换比特流。最好，Maxim



以下为原文

Hi,

thanks for your answer..

The uC is booting from the SPI flash from address 0. After the uC is initialised, I would release the SPI lines and trigger the FPGA configuration.
Of course the FPGA have to load this configuration bitstream from a higher address. This is exactly the point..

I could, of course, read the bitstream and configure the FPGA by my uC, but it would take longer because I would have to bitbang the JTAG/SPI lines..

I mean it would be great if the FPGA could grab its configuration by itself without a need to spend additional pins for JTAG, implement an XSVF interpreter and so on and I would still have the possibility to replace the bitstream by uC..

Best,
Maxim

也许是这样：
addr = 0jump to boot_addr（uC指令）ff..sync_word for FPGAmultiboot headerwith next addr of bitstreem_0 boot_addr：boot_code for uC..bitstreem_0：...



以下为原文

May be so:
 
addr = 0
jump to boot_addr (instruction for uC)
ff
..
sync_word for FPGA
multiboot header
with next addr of bitstreem_0

boot_addr:
boot_code for uC
..
bitstreem_0:
...       

嘿，
不错的想法，但我的UC不支持这个..
最好，
格言



以下为原文

Hey,Nice Idee, but my uc does not support this.. Best,Maxim

建议您再花费0.70美元购买第二个SPI内存 - 一个用于uP，另一个用于FPGA。
那你就不用再担心了。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Suggest you spend another $0.70 or so for a second SPI memory -- one for uP and one for FPGA.  Then you won't have to worry about it further.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我不确定我会打赌董事会重新调整这个但是......
如何不将MOSI线从FPGA连接到闪存，所以FPGA只能
听取闪光输出并计时。
然后让CPU发出“快速读取”命令
在使SPI线处于三态并让FPGA占用之前，在所需地址处闪存
过度。
-  Gabor
-  Gabor



以下为原文

I'm not sure I would bet a board re-spin on this but...
 
How about not connecting the MOSI line from the FPGA to the flash, so the FPGA can only
listen to the flash output and clock it.  Then have the CPU issue a "Fast READ" command
to the flash at the required address before tristating the SPI lines and letting the FPGA take
over.
 
-- Gabor
-- Gabor

很好的想法.. :)但在我这样做之前，我真的要多花一点钱..
格言



以下为原文

Nice thought.. :)  but before I do this, I really gonna spend one more flash..
 
Maxim

您是否找到了解决方案，我遇到了同样的问题....我想只使用一个内存用于uC和FPGA配置，对于固件更新，只有这个内存才更容易。
我将使用SPI模式启动uC，配置完成后，读取相同的闪存并通过uC配置FPGA和uC的第二个SPI端口，你怎么看？



以下为原文

Did you find a solution, I have the same problem....I want to use only one memory for uC and FPGA config, for firmware update it is more confortable to have only this memory.
 
I will boot the uC with SPI mode, and after configuration, read the same flash memory and configure FPGA through uC with a second SPI port of the uC, what do you think?