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我有SPC56EL70的DPM配置。我最初在调试器连接到目标时遇到了一些麻烦（可以在LSM中正常连接。）问题与不清除LSM_DPMB位有关。 Erwan发现这个常见问题解答给我留下了一些非常好的面包屑：
https://www.pls-mc.com/microcontroller-faqs/faqs-a-1291.html?sh8=bHNt 使用PLS-UDE v4.8： 1）使用已知的工作LSM模式配置连接到目标。 2）打开FLASH / OTP存储器编程工具 3）从Memory Device下拉列表中选择'SHADOW FLASH'并选中'Enable'进行连接，然后选择Exit。 4）打开一个内存窗口并导航到BIU4地址，即0x00FF_FE10 5）将地址值更改为FFBF_FFFF，该字段将显示为红色，表示它不匹配。 6）再次打开FLASH / OTP存储器编程工具，注意启用Program All按钮，然后编程并验证。 7）关闭处理器电源并重新启动。使用DPM配置/工作区重新连接，您应该能够连接到目标。从“文件”菜单中选择“加载程序”时，应该同时具有Core0和Core1二进制文件/符号。 我按照这些步骤成功地连接和dataload。在我阅读参考手册时，我不知道我所做的是否正确（即使它确实连接），位0x0040_0000不是用户选项表中描述的LSM_DPMB位。第9位，而不是第22位应该切换 LSM_DPMB。 也许BIU4地址与用户选项位的映射不同？我不知道。这似乎很深奥。问题： 我遇到的问题是，当我调试时，程序卡在SPCSetRunMode（）中等待ME.IS.R！= 0U。如果我从目标断开并重置，则程序在不调试时运行。但是，我的main_core1（）例程从未启动过。我的猜测是我没有正确配置调试，或者存在PLS - .wsx对齐问题。有人有一个wsx和一个小DPM helloworld吗？ 以上来自于谷歌翻译 以下为原文 I have a DPM configuration for SPC56EL70. I initially had some trouble getting the debugger to connect to the target ( could connect fine in LSM.) The problem had to do with not clearing the LSM_DPMB bit. Erwan found this FAQ which left me some really good bread crumbs: https://www.pls-mc.com/microcontroller-faqs/faqs-a-1291.html?sh8=bHNt Using PLS-UDE v4.8: 1) Connect to the target using a known working LSM mode configuration. 2) Open the FLASH/OTP Memory Programming Tool 3) Select 'SHADOW FLASH' from Memory Device dropdown and check 'Enable' to make the connection, then Exit. 4) Open a Memory Window and navigate to BIU4 address, which is 0x00FF_FE10 5) Change the Address value to FFBF_FFFF, and the field will be red indicating that it doesn't match. 6) Open the FLASH/OTP Memory Programming Tool again and notice that the Program All button is enabled, then program and verify. 7) Power off the processor and restart. Reconnect using a DPM configuration/workspace and you should be able to connect to the target. There should be both Core0 and Core1 binaries/symbols when Load Program is selected from the File Menu. I followed those steps with some success of being able to connect and dataload. I don't know if what I did is correct (even if it does connect) as I read the reference manual, bit 0x0040_0000 is not the LSM_DPMB bit as described in User Options Table. Bit 9, not bit 22 should toggle LSM_DPMB. Maybe the BIU4 address doesn't map the same as the User Option Bits? I don't know. It seems esoteric.The problem: The problem I am having is that when I debug, the program gets stuck in SPCSetRunMode() waiting for ME.IS.R != 0U. If I disconnect from the target and reset, then the program runs while not debugging. However, my main_core1() routine is never started. My guess is that I'm either not configured correctly to debug, or that there is a PLS - .wsx alignment issue. Does anyone have a wsx and a small DPM helloworld out there? 
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马修你好，
您是否从SPC5Studio检查了SPC56ELxx_RLA DiscoveryClus的DualCore测试应用程序？ 对于这个设备来说，这是一个很好的HelloWorld。 我在检查你的观点 “ 在我阅读参考手册时，我不知道我所做的是否正确（即使它确实连接），位0x0040_0000不是用户选项表中描述的LSM_DPMB位。第9位，而不是第22位应该切换 LSM_DPMB。 也许BIU4地址与用户选项位的映射不同？我不知道。这看起来很神秘。“ 你能给我你RM的修订版吗？ 最好的祝福 二万 以上来自于谷歌翻译 以下为原文 Hello Matthew , Did you check SPC56ELxx_RLA DualCore Test Application for DiscoveryPlus from SPC5Studio ? it is nice HelloWorld for this device. I am checking your point ' I don't know if what I did is correct (even if it does connect) as I read the reference manual, bit 0x0040_0000 is not the LSM_DPMB bit as described in User Options Table. Bit 9, not bit 22 should toggle LSM_DPMB. Maybe the BIU4 address doesn't map the same as the User Option Bits? I don't know. It seems esoteric.' Could you give me your Revision version of the RM ? Best regards Erwan |
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常见问题解答中的PLS说明并不是很好，所以和我一样，我希望尽可能多地为经验教训做出贡献。我的参考手册是RM0032 Rev 13，见表307。
对于SPC56ELxx_RLA DualCore，非常感谢。 以上来自于谷歌翻译 以下为原文 The PLS instructions from the FAQ were not very good, so like you I am hoping to contribute as much as I can on lessons learned. The reference manual I have is RM0032 Rev 13, see Table Table 307. For SPC56ELxx_RLA DualCore, many thanks. |
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嗨马修，
让我确认您启用DPM模式的过程是正确的。要设置为0的位是位9，因此要编程的值正确为0x FFBFFFFF（位位置反转bit0 ... bit31）。 启用DPM之后，我刚刚验证了我的 带有SPC56EL70L5的Leopard DiscoveryPlus板，Erwan建议的测试应用程序（SPC56ELxx_RLA DiscoveryClus的DualCore测试应用程序）工作正常。请允许我强调，为了下载并执行双核测试应用程序，必须使用特殊的cfg文件进行UDE调试，该调试在SPC56ELxx_RLA DiscoveryClus的DualCore测试应用程序中设置为默认值。 最好的祝福， 路易吉 以上来自于谷歌翻译 以下为原文 Hi Matthew, let me confirm that your procedure to enable the DPM mode is correct. The bit to be set to 0 is the bit 9, so the value to program is correctly 0x FFBFFFFF (the bit position is inverted bit0 ... bit31). After to enable the DPM, I have just verified on my Leopard DiscoveryPlus board with SPC56EL70L5 that the test application suggested by Erwan (SPC56ELxx_RLA DualCore Test Application for DiscoveryPlus) works fine. Please, let me underline that to download and execute a dual core test application, it is necessary to use a special cfg file for the UDE debug that is set as default in the SPC56ELxx_RLA DualCore Test Application for DiscoveryPlus. Best regards, Luigi |
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谢谢Luigi，我在双核运营方面也取得了很大的成功。我提供的指令工作，即使我完全不明白为什么这个特定的位
LSM_DPMB。我的猜测是BIU4寄存器没有直接映射用户选项位。 我不得不更新SPC5Studio以找到SPC56ELxx_RLA DualCore测试应用程序。另外，正如您所说，该示例应用程序中提供的debug.wsx没有任何问题。 ***非常好的工作，发布ST。 *** 以上来自于谷歌翻译 以下为原文 Thanks Luigi, I have also had a lot of success in the dual core operation. The instructions I provided work, even though I fully do not understand why that particular bit is LSM_DPMB. My guess is that the BIU4 register doesn't directly map over the the User Option Bits. I had to update SPC5Studio to find the SPC56ELxx_RLA DualCore Test Application. Also, as you said, the debug.wsx provided in that example application worked without any issues. ***Very good work getting that posted ST. *** |
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我不想让这个话题继续下去。我正在使用多个内核来决定自定义uart功能（bit-banging）。我需要在每个核心上运行PIT。我注意到在所有低级驱动程序上只实现了core0 [only]。我认为，要完全实现双核，需要在配置方案中提供核心选项。我已经实现了一些，但是当我生成时，它显然会被写入。除了初始化main_core1（）之外，lld的双核支持似乎没有实现。这是未来的实施计划吗？
干杯， 〜马特 以上来自于谷歌翻译 以下为原文 I don't want to keep this thread going. I am using multiple cores to decide up custom uart functions (bit-banging). I need a PIT to run on each core. I notice that only a core0 [only] is implemented on all of the low level drivers. I would imagine that for dual core to be fully implemented, that a core option would need to be provided in the configuration scheme. I've been implementing some, but it obviously gets written over when I generate. Other than initializing main_core1(), dual core support of the lld'sdoesn't seem to be implemented. Is this a future implementation plan? Cheers, ~Matt |
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嗨马修，
使用当前的低级驱动程序版本，您可以管理来自两个核心的所有外围设备。请注意，外围设备在2个内核之间共享，而不是重复。此外，请考虑外围中断仅由内核0（主内核）管理。 问候， 路易吉 以上来自于谷歌翻译 以下为原文 Hi Matthew, with the current low level drivers version you can manage all the peripherals from both cores. Please, note that the peripherals are shared between the 2 cores, and not duplicated. Moreover, please, take into account that the peripheral interrupts are managed only by the core 0 (Main Core). Regards, Luigi |
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那么第二个核心（Core1）不能像Core0一样运行PIT处理函数吗？
以上来自于谷歌翻译 以下为原文 So the second core (Core1) cannot run a PIT handler function like Core0 can? |
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嗨马修，
让我澄清一下我之前关于中断的反馈。当我说外围中断仅由内核0管理时，我的意思是这是SPC5Studio中的当前实现。如Leopard参考手册（中断源部分）中所述，由平台外设（例如PIT）生成的中断被路由到两个中断控制器（与核0相关的INTC_0和与核1相关的INTC_1）。特别是，在去耦并行模式下，通过在每个中断控制器上为同一个源分配不同的中断级别（中断级别0以有效禁用IRQ），可以将中断负载分配给两个内核。目前没有计划在SPC5Studio中开发此支持。 问候， 路易吉 以上来自于谷歌翻译 以下为原文 Hi Matthew, let me clarify my previous feedback about the interrupt. When I say that the peripheral interrupts are managed only by core 0, I meant that this is the current implementation in SPC5Studio. As explained in the Leopard Reference Manual (section Interrupt sources), the interrupts generate by the off-platform peripherals (e.g. PIT) are routed to both interrupt controllers (INTC_0 related to core 0 and INTC_1 related to core 1). In particular, in Decoupled Parallel Mode the interrupt load can be distributed to both cores by assigning different interrupt levels (interrupt level 0 to effectively disable an IRQ) to the same source at each interrupt controller. Currently there is no plan to develop this support in SPC5Studio. Regards, Luigi |
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我觉得我很亲密。在INTC_0中将通道2 PIT优先级设置为0可防止core0触发中断。但是，为INTC_1设置优先级对我来说还不起作用; core1从不运行PIT CH2处理程序。我猜测在初始化的某个地方，无论是组件还是定时器，我都没有完全启用INTC_1的中断器。
＆LT c取代; #define INTC_1_BASE 0x8FF48000U #define INTC_1_PSR（n）（*（（volatile uint8_t *）（INTC_1_BASE + 0x40U +（（uint16_t）（n）* sizeof（uint8_t））））） int main（void） { runCore1（）; osalThreadDelaySeconds（2）; //初始化组件 componentsInit（）; irqIsrEnable（）; //通过将优先级设置为零来禁用INTC_0的PIT2通道（这样可以防止core0运行CH2） INTC_PSR（SPC_PIT_CH2_INT_NUMBER）= INTC_PSR_ENABLE（0x00,0x00）; //通过将优先级设置为已配置的设置，为INTC_1设置PIT2通道 //（这不起作用，无法调用t_80_PIT处理程序） INTC_1_PSR（SPC_PIT_CH2_INT_NUMBER）= INTC_PSR_ENABLE（0xC0,0x04）; // ^^^注意：我在另一篇参考手册中发现0xC0用于选择核心，但我认为这些被忽略（在黑暗中拍摄） pit_lld_start（＆amp; PITD，pit_config）; pit_lld_channel_start（＆amp; PITD，1U）; pit_lld_channel_start（＆amp; PITD，2U）; //主循环 for（;;）{} } int main_core1（void） { osalThreadDelaySeconds（2）; irqIsrEnable（）; //主循环 for（;;）{} 返回0; } // t_200_PIT是由周期性中断定时器通道1调用的200kHz周期定时器 void t_200_PIT（void） { pal_lld_togglepad（PORT_D，LED_RED）; } // t_190_PIT是由周期性中断定时器通道2调用的190kHz周期定时器 void t_190_PIT（void） { pal_lld_togglepad（PORT_D，LED_GREEN）; }＆LT; / c取代; 以上来自于谷歌翻译 以下为原文 I feel like I am close. Setting the channel 2 PIT priority to 0 in INTC_0 does prevent core0 from triggering an interrupt. However, setting a priority for INTC_1 hasn't worked for me yet; core1 never runs the PIT CH2 handler. I am guessing that somewhere in the initialization, whether components or in timers, I don't fully have the interrupter for INTC_1 enabled. #define INTC_1_BASE 0x8FF48000U #define INTC_1_PSR(n) (*((volatile uint8_t *)(INTC_1_BASE + 0x40U + ((uint16_t)(n) * sizeof (uint8_t))))) int main(void) { runCore1(); osalThreadDelaySeconds(2); // initialize components componentsInit(); irqIsrEnable(); //Disable the PIT2 channel for INTC_0 by setting priority to zero (This works, prevents core0 from running CH2) INTC_PSR(SPC_PIT_CH2_INT_NUMBER) = INTC_PSR_ENABLE(0x00, 0x00); //Set the PIT2 channel for INTC_1 by setting priority to the configured setting //(This does not work, cannot get t_80_PIT handler to be called) INTC_1_PSR(SPC_PIT_CH2_INT_NUMBER) = INTC_PSR_ENABLE(0xC0, 0x04); //^^^ Note: I found in another reference manual that 0xC0 is for choosing the core, but I think these are ignored (shot in dark) pit_lld_start(&PITD, pit_config); pit_lld_channel_start(&PITD, 1U); pit_lld_channel_start(&PITD, 2U); // main loop for ( ; ; ) { } }int main_core1(void) { osalThreadDelaySeconds(2); irqIsrEnable(); // main loop for ( ; ; ) { } return 0; }// t_200_PIT is a 200kHz periodic timer called by Periodic Interrupt Timer channel 1 void t_200_PIT(void) { pal_lld_togglepad(PORT_D, LED_RED); }// t_190_PIT is a 190kHz periodic timer called by Periodic Interrupt Timer channel 2 void t_190_PIT(void) { pal_lld_togglepad(PORT_D, LED_GREEN); } |
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嗨马修，
在附件中，您可以找到用于Leopard Discovery的SPC5Studio DualCore测试应用程序的修改版本，其中PIT0（用作系统计时器）的中断由Core1管理，而SERIAL的中断由Core0管理。您可以在SPC5Studio中导入它，检查修改（在补丁文件中汇总），在您的平台上编译并执行它。在任何情况下，为了管理Core1上PIT0的中断，需要进行以下修改： 1.在文件int.c中定义用于初始化Core1中断的宏。 2.在文件systimer.c中将Core0的PIT0中断优先级设置为0（Core0上禁用PIT0中断）和Core1的SPC5_SYSTIMER_IRQ_PRIORITY。 3.在irq.c中复制与Core1相同的初始化也为Core1。 4.在文件ivor.s中定义_C1_IVOR4处理程序和函数_spr_init1（在main_core1函数中调用） 我可以进行任何其他澄清。 最好的祝福， 路易吉 以上来自于谷歌翻译 以下为原文 Hi Matthew, in attachment you can find a modified version of the SPC5Studio DualCore test application for Leopard Discovery in which the interrupts of the PIT0 (used as system timer) are managed by the Core1 while the interrupts of the SERIAL are managed by the Core0. You can import it in your SPC5Studio, check the modifications (summarized in the patch file), compile and execute it on your platform. In any case, in order to manage the interrupts of PIT0 on Core1, the following modifications are required: 1. Define in the file int.c the macro's for the initialization of the interrupts of the Core1. 2. Set in the file systimer.c the priority of the PIT0 interrupt to 0 for the Core0 (PIT0 interrupts disabled on Core0) and to SPC5_SYSTIMER_IRQ_PRIORITY for the Core1. 3. Duplicate in irq.c the same initializations made for Core0 also for the Core1. 4. Define in the file ivor.s the _C1_IVOR4 handler and the function _spr_init1 (invoked in the main_core1 function) I'm available for any other clarification. Best regards, Luigi |
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