请问在通过UART发送数据之前，我应该使用某种缓冲区来存储数据吗？

像往常一样，这是……这取决于…
如果你先通过UART检查连续发送数据，如果所有的比特都可以通过。
让我们估计：60 kSMP/s乘以12（对于开销，如停止位等），为720kbAd。这太多了，我怀疑这是否可能。
如果不连续生成数据，则YOUT数据存在上限，例如250个数据点。在这种情况下，我建议使用软件技术（循环缓冲区）来存储数据并同时发送出去。
希望有所帮助。玩得高兴
鲍勃



     以下为原文
  As usual the answere is : That depends...
    If you are continously sending your data via an UART check first if all the bits can pass.
    Let us estimate: 60 ksmp/s times 12 (for the overhead like stop-bits etc) that is 720kbaud. That's a lot and I question if that would be possible.
    If you are not continously generate data, there is an upper limit for yout data, for instance 250 data-points. In this case I would suggest to use a software- technique (circular Buffer) to store the data and to send them out concurrently.
     
    Hope that helps. Have fun
    Bob  

使用CPU将数据从ADC传输到UART将是一个耗时的过程，正如在前面的帖子中所说的那样，可能很难做到这一点。对于60kSPS，8位样本，波特需要的是60K×10位＝480 kbps。从理论上讲，PSoC Creator分量支持这个波特。在DMA的帮助下实现这一点是可能的。DMA可以被配置为具有ADCU-OUTSAMP寄存器作为源，UART TX PTR作为目的地。每个EOC都可以触发DMA来初始化这种传输。由于目标是采样2个通道，所以必须使用Amux组件（模拟硬件MUX）。在EOC的帮助下，两个模拟通道之间的切换可以自动进行。由于您打算测量2个独立的ANALOD通道，在Delsig ADC的情况下，您必须使用多采样模式。在这种模式下，最大采样率约为91 kSPS（每通道45 kSPS）。



     以下为原文
  

    

• Using CPU to transfer data from ADC to UART will be time consuming process    
  
• As told in the previous post, it might be difficult to achieve this. For 60ksps, 8 bit samples, Baud required would be 60k X 10 bits = 480 kbps. Theoritically PSoC Creator component supports this Baud. It might be possible to achieve this with the help of DMA. The DMA can be configured to have the ADC_OUTSAMP register as the source and UART TX PTR as the destination. Every EOC can trigger the DMA to intiate this transfer. Since the goal is to sample 2 channels, Amux component(Analog Hardware Mux) has to be used. Switching between the two analog channels can be automated with the help of EOC.    
  
• Since you intend to measure 2 separate analod channels, in case of Delsig ADC you have to use multisample mode. In this mode the maximum sample rate is about 91 ksps(45 ksps per channel).   
  

嗨，我有一个类似的问题出现在论坛，让我知道如果你找到一个解决方案。我正在采样一个信号到1 kSPS，并且AM通过蓝牙发送数据到115200 BPS的速度，带有TX8O-sEnDATA函数。问题是，我认为缓冲区太快，接收器不能实时工作。我希望你能帮忙。谢谢
TX8Buffel.TXT.ZIP
987字节



     以下为原文
          Hi, I have a similar problem that arises in the forum and let me know if you found a solution. I'm sampling a signal to 1 ksps and am sending the data via Bluetooth to a speed of 115200bps with TX8_SendData function. The problem is that I think the buffer is full too fast and the receiver does not work in real time. I hope you can help with this. thanks   

•   TX8Buffer.txt.zip 987 bytes  
  
  

关于你的来源的一些评论：
总是建议使用设计器“文件& GT；存档项目”在完整的项目（在正确的论坛）中发布。
你没有检查你的RX为一个字符准备好了。
在切换AMUX之后，应该丢弃下一个3个ADC值。
我看不到可能会溢出的缓冲区。
鲍勃



     以下为原文
  Some comments on your source:
    It is always advisable to post the complete project (in the right forum) using Designer "File -> Archive Project..."
    You do not check your Rx for a character beeing ready.
    After switching the AMUX the next 3 ADC-values should be discarted.
    There is no buffer I can see that may overrun.
     
    Bob

有一个使用UBFS的示例项目，描述如下：
该项目列举了作为一个8位，32 kHz，单USB音频设备的UBFS组件。音频数据通过两个DMAS传送到8位DAC。一个DMA被集成在用于发送和接收数据到存储器循环缓冲器中的UBFS组件中；另一个DMA（VDACOTDMA）将数据从存储器缓冲器移动到VDAC8。通过内部的32 kHz时钟的传入传输的同步是由软件完成的。它在循环缓冲区溢出时起作用。当内部32 kHz时钟比PC事务快时，VDACOTDMA停止一段时间来填充缓冲器。当内部32 kHz时钟比PC事务慢时，跳过一个USB传输。由于在UBFS组件中使用DMA端点内存管理，这个项目不适用于PSoC5硅。
您可以考虑使用此操作并修改示例。
问候，Dana。



     以下为原文
  There is an example project using USBFS, described as follows -
     
    This project enumerates USBFS component as a 8-bits, 32kHz, mono USB Audio Device. The audio data is passed to 8-bit DAC using two DMAs. One DMA is integrated in USBFS component used for sending and receiving data to/ from the memory cyclic buffer; the other DMA (VDACoutDMA) moves data from memory buffer to VDAC8.

The synchronization of incoming transfers with internal 32kHz clock is done by the software. It works when cyclic buffer overflows.
When internal 32kHz clock is faster compared to PC transactions, VDACoutDMA  stops for a while to fill the buffer.
When internal 32kHz clock is slower compared to PC transactions, then one USB transfer is skipped.

This project doesn't work with PSoC5 silicon due to the use of DMA Endpoint Memory Management in the USBFS component.
     
    You might consider working with this and modifying the example.
     
    Regards, Dana.