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请问我的VHDL代码有什么问题？

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问答对人有帮助，内容完整，我也想知道答案 0 您好！有谁能帮我弄清楚我的VHDL代码有什么问题？我的代码是attachemnt。以下是我尝试合成/生成编程文件时收到的警告列表... 警告：Xst：819 - “C：/VHDL_projekti/PS2K/main.vhd”第48行：过程灵敏度列表中缺少以下信号：警告：Xst：2734 - 属性“use_dsp48”不适用于此技术。警告：Xst：1710 - FF / Latch（无初始值）在块中的常量值为0。警告：Xst：1895 - 由于其他FF / Latch修整，FF / Latch（无初始值）在块中具有常量值0。警告：Xst：1895 - 由于其他FF / Latch修整，FF / Latch（无初始值）在块中具有常量值0。警告：Xst：1895 - 由于其他FF / Latch修整，FF / Latch（无初始值）在块中具有常量值0。警告：Xst：1895 - 由于其他FF / Latch修整，FF / Latch（无初始值）在块中具有常量值0。警告：Xst：1895 - 由于其他FF / Latch修整，FF / Latch（无初始值）在块中具有常量值0。警告：Xst：1710 - FF / Latch（无初始值）在块中的常量值为0。警告：Xst：1895 - 由于其他FF / Latch修整，FF / Latch（无初始值）在块中具有常量值0。警告：Xst：1895 - 由于其他FF / Latch修整，FF / Latch（无初始值）在块中具有常量值0。警告：Xst：1895 - 由于其他FF / Latch修整，FF / Latch（无初始值）在块中具有常量值0。警告：Xst：1895 - 由于其他FF / Latch修整，FF / Latch（无初始值）在块中具有常量值0。警告：Xst：1895 - 由于其他FF / Latch修整，FF / Latch（无初始值）在块中具有常量值0。警告：参数：288 - 信号reset_IBUF无负载。 PAR不会尝试路由此信号。警告：参数：283 - 此设计中有1个无负载信号。此设计将导致Bitgen发出DRC警告。警告：PhysDesignRules：367 - 信号不完整。信号有人可以帮我弄这个吗？我一直在看代码，我没有看到任何错误，但显然我做错了。 1）“过程灵敏度列表中缺少以下信号” 有人告诉我，我需要将数据信号添加到过程灵敏度列表中，这样就解决了。 2）“由于其他FF / Latch修整，块中的常量值为0” 好的，我做错了什么？我根本不想使用闩锁...... 3）“信号reset_IBUF没有负载.PAR不会尝试路由此信号。” 这是什么意思？我的重置信号有什么问题？为什么不完整？此代码是我尝试将PS / 2键盘与Spartan 3入门板配合使用。实体“键盘”执行读取并且它正常工作（当我单独测试时，我在dout信号上得到正确的扫描码（我在LED上看到它））。 rx_done是tick（20ns），表示扫描码已成功读取。我只是想知道我是否可以以某种方式识别扫描码（在我的第二个过程中我正在比较数据信号并将正确的值与segNext信号相比较）并在7段显示器上显示。当我开始工作时，我将实现正确的行为（检测所有扫描代码，检测额外的密钥以及按键和按键事件）。我不确定我是否需要描述其他任何内容，如果我这样做请留下评论:) 感谢您的帮助！！！！ mycode.vhd 2 KB 以上来自于谷歌翻译以下为原文 Hello ! Can anyone help me figure out what is wrong with my VHDL code ? My code is in attachemnt. Here is list of warnings I get when I try to synthesize it/generate programming file ... WARNING:Xst:819 - "C:/VHDL_projekti/PS2K/main.vhd" line 48: The following signals are missing in the process sensitivity list:WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .WARNING: Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.WARNING: Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.WARNING: PhysDesignRules:367 - The signal is incomplete. The signal Can someone help me with this ? I've been looking at the code and I don't see anything wrong, but obviously I'm doing something wrong. 1) "The following signals are missing in the process sensitivity list" Someone told me that I need to add data signal to process sensitivity list, so this one is solved. 2) "Due to other FF/Latch trimming, has a constant value of 0 in block" OK, what am I doing wrong ? I don't want to use latches at all ... 3) "The signal reset_IBUF has no load. PAR will not attempt to route this signal. " What does this mean ? What is wrong with my reset signal ? Why is it incomplete ? This code is my attempt at using PS/2 keyboard with Spartan 3 starter board. Entity "keyboard" does the reading and it is working properly (when I test it alone, I get correct scan codes on dout signal (I see it on LEDs)). rx_done is tick (20ns) that signals that scancode has been successfully read. I just wanted to see if I can somehow recognize the scan codes (in my second process I'm comparing data signal and putting right values to segNext signal) and display something on 7-segment display. When I get this to work, I'll then implement correct behaviour (detecting all scan codes, for extra keys and for key down and key up events). I'm not sure if I need to describe anything else, if I do please leave me a comment :) Thank you for your help !!!! mycode.vhd ‏2 KB 0
2019-6-17 08:59:52　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答举报李晓曦相关推荐 • 请问我的vhdl代码是否有故障？ 685 • 在Labview中，调用VHDL代码 3412 • 请问高手Verilog中引用VHDL原件? 1295 • verilog代码quartus II下时序仿真出现两个时钟延时，请问怎么... 6297 • 请问我能通过HPI把代码下载到它的外部扩展存储区运行吗？ 1310 • uniFlash问题 2816 • 使用CH32V307VCT6评估板上的板载WCHLink对CH565W进行调试可行吗? 648 • 请问Systemverilog中如何使用VHDL的package? 764 • ad18图都是绿色和短路 2480 • 求VHDL代码，毕业设计 2842 13个回答

答案对人有帮助，有参考价值 0 谢谢你的回复我只是初学者，很抱歉我说的任何愚蠢我曾经被告知，唯一愚蠢的问题是你没有问过的问题，所以不要感觉不好。每个人都必须从某个地方开始：smileyhappy：我没有运行模拟，因为它没有正确合成... ：smileysad：这可能是你的第一个错误。模拟它，看看会发生什么。第二个进程不同步，因为它不起作用 “它不起作用”并不是一个非常好的失败描述。你刚刚声明你没有模拟，你的代码无论如何都不会合成 - 你怎么知道结果是什么？怎么样不起作用？正如我所提到的，您需要将“数据”添加到过程敏感性列表中。所以：进程（tickDone，segReg，数据）我仍然主张让进程同步到cpand，如果需要，同步tickDone到cp。问候，霍华德 ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德在原帖中查看解决方案以上来自于谷歌翻译以下为原文 Thank you for replying I'm just beginner, so sorry for anything stupid I say I was once told that the only stupid question is the one you didn't ask, so don't feel bad. Everybody has to start somewhere :smileyhappy: I didn't run simulation because it doesn't synthetize properly... :smileysad: This is probably your first mistake. Simulate it and see what happens. Second process isn't synchronous because it doesn't work if it is "It doesn't work" is not a very good failure description. You've just stated that you haven't simulated and your code won't synthesise anyway - how do you know what the results are? What about it doesn't work? As I mentioned, you need to add "data" to your process sensitivity list. So: process (tickDone, segReg, data) I would still advocate making the process synchronous to cp and synchronising tickDone to cp if necessary. Regards, Howard ---------- "That which we must learn to do, we learn by doing." - AristotleView solution in original post

2019-6-17 09:07:59 评论举报胡丹丹

答案对人有帮助，有参考价值 0 您的模拟结果对此代码显示了什么？您需要“数据”位于第二个流程的敏感性列表中，因为它是该流程的输入。否则，您将segReg初始化为全0，然后将segNext分配给segReg，并且没有任何更改。永远。因此优化。一旦segReg优化为0，就不需要其他segReg信号，因此不需要复位，因此复位消失。第二个进程与cp不同步的原因是什么？问候，霍华德 ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德以上来自于谷歌翻译以下为原文 What do your simulation results show for this code? You would need "data" to be in the sensitivity list of your second process as it is an input to that process. Otherwise, you initialise segReg to all 0, then assign segNext to segReg and nothing changes. Ever. Hence the optimisation. Once segReg<0> is optimised to 0, there is no need for the other segReg signals and then no need for a reset, hence your reset disappears. Any reason why the second process isn't synchronous to cp? Regards, Howard ---------- "That which we must learn to do, we learn by doing." - Aristotle

2019-6-17 09:20:39 评论举报胡丹丹

答案对人有帮助，有参考价值 0 谢谢你回复:)我只是初学者，对不起我说的任何愚蠢:) 我没有运行模拟，因为它没有正确合成... 为什么segReg总是0？如果tick是1，我正在改变segNext ... 第二个过程不是同步的，因为它不起作用，如果它......我在一本书中看到了类似的东西（尽管它在FSMD中使用过，但我认为它可以工作）。无论如何，你能告诉我如何在tick为高时比较数据信号，然后将相应的值设置为segReg（或段输出）？谢谢！！！！以上来自于谷歌翻译以下为原文 Thank you for replying :) I'm just beginner, so sorry for anything stupid I say :) I didn't run simulation because it doesn't synthetize properly... Why is segReg always 0 ? I'm changing segNext if tick is 1 ... Second process isn't synchronous because it doesn't work if it is ... And I saw something like this in one book (although it was used in FSMD, but I thought it could work). Anyway, can you tell me how can I compare data signal when tick is high and then set appropriate value to segReg (or segments output) ? Thanks !!!!

2019-6-17 09:35:38 评论举报周灿金

答案对人有帮助，有参考价值 0 谢谢你的回复我只是初学者，很抱歉我说的任何愚蠢我曾经被告知，唯一愚蠢的问题是你没有问过的问题，所以不要感觉不好。每个人都必须从某个地方开始：smileyhappy：我没有运行模拟，因为它没有正确合成... ：smileysad：这可能是你的第一个错误。模拟它，看看会发生什么。第二个进程不同步，因为它不起作用 “它不起作用”并不是一个非常好的失败描述。你刚刚声明你没有模拟，你的代码无论如何都不会合成 - 你怎么知道结果是什么？怎么样不起作用？正如我所提到的，您需要将“数据”添加到过程敏感性列表中。所以：进程（tickDone，segReg，数据）我仍然主张让进程同步到cpand，如果需要，同步tickDone到cp。问候，霍华德 ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德以上来自于谷歌翻译以下为原文 Thank you for replying I'm just beginner, so sorry for anything stupid I say I was once told that the only stupid question is the one you didn't ask, so don't feel bad. Everybody has to start somewhere :smileyhappy: I didn't run simulation because it doesn't synthetize properly... :smileysad: This is probably your first mistake. Simulate it and see what happens. Second process isn't synchronous because it doesn't work if it is "It doesn't work" is not a very good failure description. You've just stated that you haven't simulated and your code won't synthesise anyway - how do you know what the results are? What about it doesn't work? As I mentioned, you need to add "data" to your process sensitivity list. So: process (tickDone, segReg, data) I would still advocate making the process synchronous to cp and synchronising tickDone to cp if necessary. Regards, Howard ---------- "That which we must learn to do, we learn by doing." - Aristotle

2019-6-17 09:44:25 评论举报胡丹丹

答案对人有帮助，有参考价值 0 在快速检查您发布的代码后，我没有看到任何明显的结果。不过这个如果“键盘”实体中存在导致问题的问题，可能会发生条件tickDone ='1'且data = x“16”永远不会发生。关于灵敏度列表中缺少的项目的注释实际上不会影响合成，即XST将添加缺失的项目以使该过程正确组合。然而因为模拟，它会导致模拟和合成之间的不匹配只会在列表中的项目发生变化时触发流程。无论如何我不这么认为是信号修整的原因。我会查看键盘模块的问题。 - Gabor - Gabor 以上来自于谷歌翻译以下为原文 I didn't see anything obvious after a quick check of the code you posted. However this could happen if there are problems in the "keyboard" entity which would cause the condition tickDone = '1' and data = x"16" never to happen. The note about items missing from the sensitivity list doesn't actually affect synthesis, i.e. XST will add the missing items to make the process properly combinatorial. However it will cause a mismatch between simulation and synthesis because the simulation will only trigger the process when items in the list change. In any case I don't think this is the cause of the signal trimming. I would look into the keyboard module for the problem. -- Gabor -- Gabor

2019-6-17 09:52:22 评论举报杨玲

答案对人有帮助，有参考价值 0 请通过将层次结构设置为软来检查是否收到相同的警告。以上来自于谷歌翻译以下为原文 Please check by setting the hierarchy to soft whether you get the same warning.

2019-6-17 10:03:18 评论举报陈强

答案对人有帮助，有参考价值 0 “我仍然主张让这个过程与cp同步”我认为O / P正在尝试一种“2进程FSM”设计，受到一些人的喜爱，被其他人弃用。 ------------------------------------------“如果它不起作用模拟，它不会在板上工作。“ 以上来自于谷歌翻译以下为原文 "I would still advocate making the process synchronous to cp" I think the O/P is attempting a "2-process FSM" design, beloved by some, deprecated by others. ------------------------------------------ "If it don't work in simulation, it won't work on the board."

2019-6-17 10:15:46 评论举报李刚

答案对人有帮助，有参考价值 0 关于灵敏度列表中缺少的项目的注释实际上不会影响合成，即XST将添加缺失的项目以使该过程正确组合。 Gabor - 感谢对此主题的更正。这我不知道（或没有经历过）。在理论上（而不是学术上），如果合成器能够做到这一点，从综合的角度来看，灵敏度列表的重点是什么？合成器可以添加多少“缺失的项目”？ ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德以上来自于谷歌翻译以下为原文 The note about items missing from the sensitivity list doesn't actually affect synthesis, i.e. XST will add the missing items to make the process properly combinatorial. Gabor - thanks for the correction on this subject. This I did not know (or have not experienced). On a theoretical (and rather academic) note, if the synthesiser can do this, what is the point of the sensitivity list from a synthesis point of view? How many "missing items" can the synthesiser add? ---------- "That which we must learn to do, we learn by doing." - Aristotle

2019-6-17 10:21:28 评论举报胡丹丹

答案对人有帮助，有参考价值 0 在理论上（而不是学术上），如果合成器能够做到这一点，从综合的角度来看，灵敏度列表的重点是什么？合成器可以添加多少“缺失的项目”？灵敏度列表确定（或帮助确定）合成器的时钟（与组合）过程以及同步与异步设置/重置。我不确定这对VHDL有多大适用，但在Verilog语言中，“posedge”与“negedge”结构在灵敏度列表中而不是在过程的主体中。对于组合过程，综合工具并不关心 - 但模拟器应使用过程敏感性列表来安排过程的“评估”。适当选择的灵敏度列表应该改善（缩短）模拟运行的挂钟时间。 - 鲍勃埃尔金德签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。阅读手册或用户指南。你读过手册了吗？你能找到手册吗？2。搜索论坛（并搜索网页）以寻找类似的主题。不要在多个论坛上发布相同的问题。不要在别人的主题上发布新主题或问题，开始新的主题！5。学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。提供有用的详细信息（请与网页，数据表链接）.7。您的代码中的评论不需要支付额外费用。我没有支付论坛帖子的费用。如果我写一篇好文章，那么我一无所获。以上来自于谷歌翻译以下为原文 On a theoretical (and rather academic) note, if the synthesiser can do this, what is the point of the sensitivity list from a synthesis point of view? How many "missing items" can the synthesiser add? The sensitivity list determines (or helps determine) a clocked (vs. combinatorial) process and synchronous vs. async set/reset -- for the synthesiser. I'm not sure how much this applies to VHDL, but in Verilog language the "posedge" vs. "negedge" construct is in the sensitivity list rather than in the main body of the process. For combinatorial processes, the synthesis tool does not care -- but the simulator should use the process sensitivity list for scheduling the 'evaluation' of the process. A properly selective sensitivity list should improve (shorten) wall clock time for simulation runs. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

2019-6-17 10:26:32 评论举报张晓宁

答案对人有帮助，有参考价值 0 在理论上（而不是学术上），如果合成器能够做到这一点，从综合的角度来看，灵敏度列表的重点是什么？合成器可以添加多少“缺失的项目”？合成器对世界的看法是通过一组“模板”来匹配可用的逻辑结构。与模拟器不同，它的功能受到限制。对于组合逻辑，合成器有效地使用“全部”（如在VHDL 2008中）用于灵敏度列表。这使得更容易在硬件中生成逻辑而不尝试匹配奇怪的顺序行为列表中缺少的项目暗示。如果列表中没有所有RHS项目，合成器会警告您硬件可能与模拟不匹配。来自学术界从某种角度来看，合成器的工作是创建与模拟行为相匹配的硬件。当合成器不能做到这一点，而不是举手和停止，它只是警告你它不能完全匹配模拟行为，并尽力做到最好。那里在某些情况下，例如具有多个“事件条件”的流程，其中很清楚用户希望代码产生一种奇怪的顺序行为。在那些情况下你将从综合而不是警告中获得错误。对于XST，这些错误看起来像“糟糕” 顺序描述。“ 我通常在Verilog中编写所有代码，它相当于VHDL 2008“all” 喜欢：总是@ * 开始。。。结束这相当于：总是@（a，b，c，...）开始结束其中（a，b，c，...）将是方程右侧的所有元素除了多维数组（存储器）。 - Gabor - Gabor 以上来自于谷歌翻译以下为原文 On a theoretical (and rather academic) note, if the synthesiser can do this, what is the point of the sensitivity list from a synthesis point of view? How many "missing items" can the synthesiser add? The synthesizer's view of the world is through a set of "templates" which it matches to available logic structures. Unlike the simulator, it is limited in what it can achieve. For combinatorial logic, the synthesizer effectively uses "all" (as in VHDL 2008) for the sensitivity list. This makes it easier to generate logic in hardware without trying to match the wierd sequential behavior implied by missing items in the list. When you don't have all of the RHS items in the list, the synthesizer will warn you that your hardware may not match simulation. From the academic point of view, a synthesizer's job is to create hardware that matches the behavior in simulation. When the synthesizer can't do that, rather than throwing up its hands and stopping, it just warns you that it can't exactly match the simulation behavior and does the best it can. There are some cases, for example processes with more than one 'event condition, where it is clear that the user intended the code to produce a wierd sequential behavior. In those cases you will get an error from synthesis instead of the warning. For XST these errors look like "bad sequential description." I generally write all my code in Verilog, which has the equivalent of the VHDL 2008 "all" like: always @* begin . . . end This is equivalent to: always @ (a, b, c, ...) begin end Where (a, b, c, ...) would be all of the elements on the right-hand side of the equations with the exception of multidimensional arrays (memories). -- Gabor -- Gabor

2019-6-17 10:38:18 评论举报杨玲

答案对人有帮助，有参考价值 0 Gabor，鲍勃 - 感谢两位解释。 VHDL（而不是Verilog），我想我可以在较小的程度上管理它。理解合成器如何做它的功能一直都是一个谜。我觉得更近了一步：笑笑：这可以解释，特别是在我早期的HDL中，为什么我不能完全实现我想要的东西并且有很多头疼。你永远不会停止学习：smileyhappy： ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德以上来自于谷歌翻译以下为原文 Gabor, Bob - thanks both for the explanations. VHDL (rather than Verilog), I think I can manage, to a lesser degree, perhaps. Understanding how the synthesiser does what it does has always been a bit of a mystery. I feel one step closer :smileyhappy: This may explain, particularly in my early days of HDL, why I couldn't quite achieve what I wanted and had a lot of head scratching. You never stop learning :smileyhappy: ---------- "That which we must learn to do, we learn by doing." - Aristotle

2019-6-17 10:54:02 评论举报胡丹丹

答案对人有帮助，有参考价值 0 “正确选择的灵敏度列表应该改善（缩短）模拟运行的挂钟时间。”在模拟（VHDL）中，具有缺失信号的过程灵敏度列表将不会按照您的预期/期望的方式进行模拟。如果有额外的信号，可能需要更长的时间（以挂钟为单位）。 ------------------------------------------“如果它不起作用模拟，它不会在板上工作。“ 以上来自于谷歌翻译以下为原文 "A properly selective sensitivity list should improve (shorten) wall clock time for simulation runs." In simulation (of VHDL), a process sensitivity list with missing signals will not simulate in the way you intend/expect. If there are extra signals, it will probably take longer (in wall clock units). ------------------------------------------ "If it don't work in simulation, it won't work on the board."

2019-6-17 11:01:02 评论举报李刚

答案对人有帮助，有参考价值 0 嗨!! 首先，我很抱歉没有回答这么长时间......我的学习工作很多，所以我没有时间花在学习VHDL上。其次，我很抱歉:)我的问题是由键盘实体引起的，虽然我认为它很完美......我在FSM中输了错字。这是拼写错误的代码片段： case cState是。。。当stop => 如果ps2cFalling ='1'那么 NSTATE NSTATE 如您所见，从未调用状态加载，并且从未为rx_done tick分配值1。特别感谢tohgleamon1提醒我做模拟（我永远不会忘记;））以及回复此主题的所有其他人并与我们分享他们的知识:)我从每个帖子中学到了新东西！以上来自于谷歌翻译以下为原文 Hi !! Firstly, I'm very sorry for not responding for such a long time ... I've had much work related to my studying, so I didn't have time to spend on learning VHDL. Secondly, I'm sorry again :) My problem was caused by keyboard entity, although I thought it was perfect ... I had typo in FSM. Here is the piece of the code with the typo: case cState is... when stop => if ps2cFalling = '1' then nState <= load; end if; when load => nState <= idle; rx_done <= '1';end case; As you can see, state load was never called, and rx_done tick was never assigned the value of 1. Thanks especially to hgleamon1 for reminding me to do simulation (I'm never going to forget that ;) ) and also to all other people who replyed to this thread and shared their knowledge with us :) I've learned something new from every post !

2019-6-17 11:06:25 评论举报周灿金

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