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我对coregen Clocking Wizard，v3.2有疑问。
我试图对S6中PLL的输出抖动进行半精确估计。 数据表说引用向导。 这是我们的场景： -Spartan6 - 我们的输入来自高度精确的19.2 MHz振荡器，+ / - 0.5 ppm。 - 我们希望通过PLL生成27 MHz输出，输出抖动尽可能小（最高+/- 50 ppm，约为3.7 ps） 当我使用向导时，它似乎对第1页上的输入抖动的非常低的值不敏感。例如，如果我为输入抖动规范设置了1ps的值，它甚至似乎都没有更新 输出时钟正常（仍然显示100MHz的原始输出）。 如果我输入100ps的值，那么我可以将时钟更新为27MHz，但它显示的输出抖动约为280ps。 这对于我们在应用程序中需要的内容来说非常高。 当我把它放回到1ps或10ps时，它似乎对输出结果没有影响。 所以我的问题是： GUI的输入抖动值是否有问题？ 它是否正确使用它们？ 计算仅对输入抖动> 100 ps左右有效吗？ 或者输出抖动是否有一个固定的阈值，我们永远不会得到它？ 如果有人之前已经看过这个或者可以提供有关时钟向导准确性的任何细节，我会很感激。 谢谢！ 以上来自于谷歌翻译 以下为原文 I have a question regarding the coregen Clocking Wizard, v3.2. I'm trying to get a semi-accurate estimate for the output jitter of a PLL in S6. The datasheet says to reference the wizard. Here's our scenario: -Spartan6 -Our input is from a highly accurate 19.2 MHz oscillator, +/- 0.5 ppm. -We want to generate a 27 MHz output, presumably via PLL, with as little output jitter as possible (up to +/-50 ppm, which would be about 3.7ps) When I use the wizard, it doesn’t seem to be sensitive to very LOW values on input jitter on page 1. For example, if I put a value of 1ps for the input jitter spec, it doesn’t even seem to update the output clock properly (still shows the original output of 100MHz). If I put a value of 100ps, then I can get it to update the clock to 27MHz, but it shows an output jitter of about 280ps. That’s very high for what we’d need in our application. When I put it back down to 1ps or 10ps, it seems to have no impact on the output results. So my question is this: Is there a problem with the GUI for low values of input jitter? Does it use them properly? Are the calculations only valid for input jitter > 100 ps or so? Or is there a fixed threshold on the output jitter that we are never going to get below? If anyone has seen this before or can provide any details on the accuracy of the Clocking Wizard, I'd appreciate it. Thanks! 
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Ĵ，
对于这些值，测量峰值到峰值的抖动。 CMOS中的逆变器中的峰峰值抖动（没有别的）最多为25ps p-p。 所以，是的，任何低于100 ps的东西都会因此而异常好（并且很难实现）。 并且，ppm与抖动无关，因此我不知道您的时钟源的抖动是什么。 如果没有指定，那么我怀疑它本身是50到150 ps p-p（或更差）。 请记住，您所做的任何不完美的事情（信号完整性设计，最小化同时切换，完美的去耦或旁路，完美的PCB设计）都会使p-p抖动倍增。 “低抖动”极难实现，通常只有具有多年经验的人才能实现。 这就像说“没有噪音”它不会经常发生 - 总是有噪音！ 我听说有关抖动，从DC到时钟速率，或无限的抖动频谱。 如果你可以忍受快速抖动或慢抖动，那么有些技巧可以帮助你满足要求。 Austin Lesea主要工程师Xilinx San Jose 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 j, Jitter is measured in peak to peak for these values. Peak to peak jitter in an inverter in CMOS (nothing else) is at best 25ps p-p. So yes, anything below 100 ps will be exceptionally good as a result (and very hard to acheive). And, ppm has nothing to do with jitter, so I have no idea what the jitter of your clock source is. If it isn't specified, then I suspect it itself is from 50 to 150 ps p-p (or worse). Remember, anything you do that isn't perfect (signal integrity design, minimize simultaeneous switching, perfect decoupling or bypass, perfect pcb design) will multiply the p-p jitter. "low jitter" is extremely difficult to acheive, and usually is only accom[plished by someone with years of experience. It is like saying "no noise" it just doesn't happen often -- there is always noise! I am hear talking about jitter, from DC to the clock rate, or unbounded frequency spectrum of jitter. If you can tolerate fast jitter, or slow jitter, there are tricks tht can help you meet the requirements. Austin Lesea Principal Engineer Xilinx San JoseView solution in original post |
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Ĵ，
对于这些值，测量峰值到峰值的抖动。 CMOS中的逆变器中的峰峰值抖动（没有别的）最多为25ps p-p。 所以，是的，任何低于100 ps的东西都会因此而异常好（并且很难实现）。 并且，ppm与抖动无关，因此我不知道您的时钟源的抖动是什么。 如果没有指定，那么我怀疑它本身是50到150 ps p-p（或更差）。 请记住，您所做的任何不完美的事情（信号完整性设计，最小化同时切换，完美的去耦或旁路，完美的PCB设计）都会使p-p抖动倍增。 “低抖动”极难实现，通常只有具有多年经验的人才能实现。 这就像说“没有噪音”它不会经常发生 - 总是有噪音！ 我听说有关抖动，从DC到时钟速率，或无限的抖动频谱。 如果你可以忍受快速抖动或慢抖动，那么有些技巧可以帮助你满足要求。 Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 j, Jitter is measured in peak to peak for these values. Peak to peak jitter in an inverter in CMOS (nothing else) is at best 25ps p-p. So yes, anything below 100 ps will be exceptionally good as a result (and very hard to acheive). And, ppm has nothing to do with jitter, so I have no idea what the jitter of your clock source is. If it isn't specified, then I suspect it itself is from 50 to 150 ps p-p (or worse). Remember, anything you do that isn't perfect (signal integrity design, minimize simultaeneous switching, perfect decoupling or bypass, perfect pcb design) will multiply the p-p jitter. "low jitter" is extremely difficult to acheive, and usually is only accom[plished by someone with years of experience. It is like saying "no noise" it just doesn't happen often -- there is always noise! I am hear talking about jitter, from DC to the clock rate, or unbounded frequency spectrum of jitter. If you can tolerate fast jitter, or slow jitter, there are tricks tht can help you meet the requirements. Austin Lesea Principal Engineer Xilinx San Jose |
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奥斯汀，非常感谢你的回复。
我是一名FPGA设计师，试图回答模拟人的一些问题，所以很明显我不在我的元素中！ :) 所以听起来我做了一些不正确的假设，振荡器容差与其抖动规格之间存在任何关联。 既然情况并非如此，那么让我回到我的基本问题： - 具有19.2MHz振荡器，精度为+/- 0.5ppm，PLL能否产生27MHz的输出时钟，精度优于+/- 50ppm？ - 时钟向导或数据表是否提供了输出时钟精度的规格，单位为ppm？ 有没有办法让我推断出这个价值？ 对这些问题的想法将不胜感激。 再次感谢， 约翰 以上来自于谷歌翻译 以下为原文 Austin, thank you very much for your response. I'm an FPGA designer trying to answer some questions for an analog guy, so clearly I'm out of my element! :) So it sounds like I was making some incorrect assumptions, that there's any correlation between the oscillator tolerance and its jitter spec. Since that's not the case, let me get back to my basic overall question: -With a 19.2MHz oscillator with +/- 0.5ppm accuracy, can the PLL produce an output clock at 27MHz with better than +/- 50 ppm accuracy? -Does the clock wizard or datasheet provide a spec as to the accuracy of the output clock in ppm? Is there a way for me to infer this value? Thoughts on those questions would be greatly appreciated. Thanks again, John |
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对于锁定的PLL，频率容差始终是相同的输入到输出。
但是，PLL总是会增加一些抖动，通常指定为+/- J ps。 如果您想知道瞬时最小和最大PLL时钟周期，那么从默认周期中提取/添加频率容差和抖动值是一件简单的事情。 然而，这些最小和最大瞬时周期是否与您的系统有任何关系是完全不同的。 ------------------------------------------“如果它不起作用 模拟，它不会在板上工作。“ 以上来自于谷歌翻译 以下为原文 With a locked PLL, the frequency tolerance is always the same input-to-output. However, the PLL always adds some jitter, which is usually specified as +/- J ps. If you want to know the instantaneous minimum and maximum PLL clock periods, then it is a simple matter of subrtacting/adding both the frequency tolerance and jitter values from the default period. Whether these minimum and maximum instantaneous periods are of any relevance to your system is an entirely different matter, however. ------------------------------------------ "If it don't work in simulation, it won't work on the board." |
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- 具有19.2MHz振荡器，精度为+/- 0.5ppm，PLL能否产生27MHz的输出时钟，精度优于+/- 50ppm？
锁定PLL的输出不应与源时基的长期精度不同 - 输入和输出精度应匹配。 只有短期精度（即抖动）才是问题。 使用时钟向导，您可以从19.2MHz生成27MHz，乘数为45，分频器为32。 - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 -With a 19.2MHz oscillator with +/- 0.5ppm accuracy, can the PLL produce an output clock at 27MHz with better than +/- 50 ppm accuracy? The output of a locked PLL should not differ from the longterm accuracy of the source timebase -- input and output accuracy should match. Only the short-term accuracy (i.e. jitter) might be an issue. Using the Clocking Wizard, you can generate 27MHz from 19.2MHz with a multiplier of 45 and a divider of 32. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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谢谢大家的详细回复。
这给了我关闭我的问题所需的信息。 约翰 以上来自于谷歌翻译 以下为原文 Thank you all for the detailed responses. That gave me the info I needed to close out my question. John |
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