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我对Spartan 3 FPGA的乘法有一些疑问。 Spartan 3包含多达104个专用乘法器。 显然我可以选择管道这些乘法器(例如,系统生成器的“复数乘法3.1”块为我提供了这个机会,此外,所提到的块的数据表包含与乘法速度和流水线级数量相关的表格。 )。 我在18x18bit乘法器上使用17x17bit信号进行了一些测试,以查看流水线级和速度之间的关系,以找到我设计的最佳级数。 结果很奇怪。 在综合报告中,最坏情况路径时间随着阶段数量的增加而减少(对我来说听起来合乎逻辑),同时定时报告显示0个管道乘法的不合理1-2ns的最坏情况路径和1个合理的10-15ns或者 2阶段流水线。 但是,应用更多的管道并没有帮助提高速度,相反,速度随着更多阶段而降低..(所有这些应用相同的端口映射和ucf文件用于生成过程) 现在我的问题 a)是专用的乘法器,设计用于管道,还是这个选项而不是基于LUT的乘法架构? 这至少可以解释为什么在使用专用乘法器时提高流水线等级不会提高速度。 b)最好的解决方案是让System Generator自己选择阶段数量。 这里的问题是我看不到插入了多少个阶段。 因此,我无法在适当的时间内延迟与乘法器并行的路径。 我在哪里可以看到使用了多少个阶段? 顺便说一句。 我正在使用ISE 13.4和matlab 2012a 问候 baesae 以上来自于谷歌翻译 以下为原文 Hey there I do have some questions regarding multiplication on Spartan 3 FPGAs. Spartan 3 contains up to 104 dedicated multipliers. Apparently I can chose to pipeline these multipliers (I. e. the 'Complex Multiplication 3.1' block of System Generator offers me this opportunity, furthermore the datasheet of the mentioned block contains tables relating the speed of the multiplication and the amount of pipelining-stages). I made some tests to see the relation between pipelining stages and speed using a 17x17bit signal on the 18x18bit multiplier to find the optimal amount of stages for my design. The result was strange. In the synthesis report the worst case path time decreased with increasing amount of stages (what sounds logical to me), meanwhile the timing report displayed worst case paths of unreasonable 1-2ns for the 0 piped-multiplication and reasonable 10-15ns for 1 or 2 stages pipelining. but still, applying more pipes did not help to increase speed, contrariwise the speed decreased with more stages.. (all this applying the same port map and ucf-file for generation-process) Now my questions a) are dedicated multipliers designed to be piped or is this option rather for the LUT based multiplication architecture? This would at least explain why enhancing grade of pipelining does not enhance speed when using dedicated multipliers. b) The nicest solution would be to let System Generator chose the amount of stages by itself. Problem here is I cannot see how many stages were inserted. Thus I cannot delay the paths parallel to the multipliers for the appropriate time. Where can I see how many stages were used? btw. I'm using ISE 13.4 and Matlab 2012a Regards baesae |
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3个回答
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综合时序报告是不可靠的。只有Post-PAR时序报告是可靠的。
------------------------------------------“如果它不起作用 模拟,它不会在板上工作。“ 以上来自于谷歌翻译 以下为原文 Synthesis Timing Reports are unreliable. Only the Post-PAR Timing Report is reliable. ------------------------------------------ "If it don't work in simulation, it won't work on the board." |
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感谢您的回答。
对不起,那里不太清楚。 通过“时序报告”,我在'设计 - 总结 - >后PAR静态时序'中打开PAR之后打开的后PAR时序报告 显然,对于零延迟专用乘法,合成器移除整个分量(否则,不能通过'后PAR定时报告'报告1-2ns最坏情况路径......)。 我问自己:为什么合成器应该在没有延迟的情况下移除组件,但是在环境保持不变的情况下,不能使用1或2个延迟/管道。 最重要的是:当我让System Generator选择理想的管道数时,我在哪里可以找到System Generator中的管道级数? :) 以上来自于谷歌翻译 以下为原文 Thanks for your answer. Sorry, wasn't very clear there. By "timing report" I ment the Post-PAR Timing Report I opened after PAR in 'Design-Summary -> Post-PAR Static Timing' Apparently for a zero delay dedicated multiplication, the synthesizer removes the whole component (otherwise 1-2ns worst case paths reported by 'Post-PAR Timing Report' are not possible..). I ask myself: Why should the synthesizer remove the component with zero delay, but not with 1 or 2 delays/pipes, eventhough the environment stays the same. And most important: where can I find the number of pipe stages in System Generator when I let System Generator select the ideal number of pipes? :) |
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从未使用过System Generator。希望其他人可以帮助你,但该工具的专家往往会潜伏在“DSP工具”论坛中。
------------------------------------------“如果它不起作用 模拟,它不会在板上工作。“ 以上来自于谷歌翻译 以下为原文 Never used System Generator. Hopefully, someone else can help you, but the experts for that tool tend to lurk in the 'DSP Tools' forum. ------------------------------------------ "If it don't work in simulation, it won't work on the board." |
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