[问答]

PC命令使电路板过载

1516

问答对人有帮助，内容完整，我也想知道答案 0 你好设计如下（i）.FPGA通过UART等待来自PC的数据（ⅱ）。从PC接收数据（三）。通过验证保留关键字，检查PC是否已完全传输数据（iv）.FPGA等待来自PC的命令将数据传输回PC （v）。停止状态后路线模拟工作正常，满足所有约束条件我实现设计后遇到了问题。电路板由设置为6.0 V和400 mA的电源供电。我也使用FTDI芯片与PC接口一旦我开始从PC发送数据，输入电压下降到3.9 V，电流达到430 mA。我在UART的另一个设计中使用了相同的FTDI芯片，没有这样的问题 HDL设计是否会使电路板过载？。任何帮助，将不胜感激？谢谢费萨尔以上来自于谷歌翻译以下为原文 Hi Design is as follows (i).FPGA waits for data from PC via UART (ii). Receives the data from PC (iii). Check whether PC has transferred the data completely by verifying the reserved keyword (iv).FPGA Wait for command from the PC to transfer the data back to PC (v).Stop state Post route simulation works fine and all the constraints met I have encountered a problem once I implement the design. Board is powered from a power supply with settings 6.0 V and 400 mA. Also I am using FTDI chip to interface with PC Once I start to send the data from PC, Input voltage drops down to 3.9 V and current reaches 430 mA. I have used same FTDI chip in another designs with UART, No such problems Does HDL design makes the board over loaded ? . Any help would be appreciated ? Thanks Faisal 0
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答案对人有帮助，有参考价值 0 谢谢Bob，我正在使用的板有XC3S200 TQ144，ADC（10位），PS RAM和GPS接收器。我使用的电源是TTI EL302D双电源，具有过流截止功能从PC到FPAGA的数据传输过程中功耗很高。但是，当FPGA将数据传输回PC时，功耗很低。 FTDI芯片和电路板接地是连接的。设计工作正常。我是逐字节地从PC发送数据。在PC中每个字节后我都引入了1秒的时间延迟。 “万一你无意中在你的身上造成了很大的潮流状况设计（例如两个连接的输出同时驱动HIGH和LOW）“ 我猜这种情况与串口中的数据传输相匹配，应该有高和低的交替变化（3.3 V＆amp; 0 V）。但是与振荡器的输入时钟相比，这种变化的频率太低了。我不确定PC和电路板之间是否存在阻抗误匹配。但是，互连电缆的长度要短得多，电路板和PC之间的数据传输频率约为0.5 MHz 你的猜测是正确的。是的我是来自英国格拉斯哥斯特拉斯克莱德大学的学生。我不属于巴基斯坦。你有没有在英国大学讲课？。最好的祝福费萨尔以上来自于谷歌翻译以下为原文 Thanks Bob, Board I am working with has XC3S200 TQ144 , ADC (10 bit) , PS RAM and GPS receiver. Power supply I am using is TTI EL302D dual power supply with over current cutoff Power consumption is high during the data transfer from PC to FPAGA. But power consumption is low when FPGA transfer the data back to PC. FTDI chip and board ground are connecetd. Design is working fine. I am sending the data from PC as byte by byte. In the PC After every byte I have introduced a time delay of 1 sec. "In case you have inadvertently created a high current condition in your design (e.g. two connected outputs simultaneously driving HIGH and LOW) " I guess this scenario matches with data transmission in the serial port , there should be alternate change of high and low (3.3 V & 0 V) . But this changing frequency is too low compared with input clock from the oscillator. I am not sure whether any impedance mis match occurs between PC and board . But the length of inter connecting cable is much shorter and the frequency of data tranfer between board and PC is around 0.5 MHz Your guessing is correct. Yes I am a student from University of Strathclyde , Glasgow , United Kingdom . I am not belonging to Pakistan. Did you give any lectures in UK Universities ? . Best Regards Faisal

2019-5-31 14:57:09 评论举报卿洁